Method for driving semiconductor device having capacitive load, method and apparatus for driving load, and electronic apparatus

ABSTRACT

When a signal is read from a CCD solid-state image pickup element, the CCD solid-state image pickup element is driven with at least two driving voltages so that high-speed reading is performed with generation of noise due to interference between the driving voltages reduced. The CCD solid-state image includes a charge storage section between a vertical transfer register and a horizontal transfer register. By performing the transfer of charge in the direction of columns during an effective transfer period of the transfer in the direction of rows, signal charge of one row generated by a light receiving sensor is transferred to the charge storage section, and by performing the transfer outside the effective transfer period in the transfer in the direction of the row, the signal charge of one row transferred to the charge storage section is transferred to the horizontal transfer register.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese PatentApplication JP 2005-286061 filed in the Japanese Patent Office on Sep.30, 2005, and Japanese Patent Application JP 2006-038448 filed in theJapanese Patent Office on Feb. 15, 2006, the entire contents of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and device for driving asemiconductor device having a capacitive load such as a drivingelectrode of a two-dimensional matrix of charge-coupled device (CCD)solid-state image pickup elements, an electronic apparatus implementingthe driving method and apparatus. More specifically, the presentinvention relates to an image pickup device achieving a high-speed framerate in the reading of a signal. Furthermore, the present inventionrelates to a driving method and driving device for driving a load ofcapacitive reactance or a load of inductive reactance and an electronicapparatus implementing the driving method and device. More specifically,the present invention relates to a mechanism for reducing a variety oftypes of variations and environmental variations so that a load outputsignal mildly changes when pulse driving is performed at a predeterminedtransient speed.

2. Description of the Related Art

There is a mounting need for high-speed image capturing and then slowplayback on a video camera incorporating a CCD solid-state image pickupelement regardless of television system. Users are concerned with a dropin continuous shooting speed in digital still cameras incorporating theCCD solid-state image pickup element as the number of pixels increases.A need for high-speed image pickup element is thus mounting.

Electronic circuits and electronic apparatuses employ a variety ofmechanisms for driving a load having an impedance component with a pulsesignal.

For example, image pickup devices having a two-dimensional matrix of CCDsolid-state image pickup elements, each containing a transfer electrodeserving as a capacitive reactance, are widely used. Motors havingwinding coils serving as an inductive reactance are also used.

An impedance component such as a capacitive reactance or an inductivereactance as a load is typically driven by a pulse signal. Phase andtransient characteristic of the driving pulse are affected by arelationship between the load and the driving element, morespecifically, variations in the load, variations in performance of theelement, and environmental variations. As a result, the load cannot beappropriately driven. At low speed driving, the effect of phase andtransient characteristic variations may be marginal, but at high speeddriving, a small amount of variation leads to large performancevariation.

For example, when a plurality of loads are driven by pulse signalsslightly shifted one after another in phase, appropriate driving cannotbe performed. When two loads are driven by reverse phased drivingsignals, a slight phase different between the driving signals leads toinappropriate driving.

Specific examples are described below. There is a mounting need forhigh-speed image capturing and then slow playback on a video cameraincorporating a CCD solid-state image pickup element regardless oftelevision system. Users are concerned with a drop in continuousshooting speed in digital still cameras incorporating the CCDsolid-state image pickup element as the number of pixels increases. Aneed for high-speed image pickup element is thus mounting.

FIGS. 22A and 22B illustrate a mechanism of a known image pickup device.FIG. 22A illustrates a major portion of the known image pickup deviceemploying a CCD solid-state image pickup element implementing interlinetransfer (IT) system. FIG. 22B illustrates a driving method of the CCDsolid-state image pickup element.

The known image pickup device 3 includes a CCD solid-state image pickupelement 30, and a driving circuit 4 for driving the CCD solid-stateimage pickup element 30.

The CCD solid-state image pickup element 30 includes a two-dimensionalmatrix (rows by columns) of a plurality of light receiving sensors 31serving as pixels, and an image pickup section (light receiving section)30 a having vertical transfer registers 33 having a plurality of CCDstructures corresponding to the light receiving sensors 31. Horizontaltransfer registers 34, each having a CCD structure, connected to thefinal stage of each vertical transfer register 33 are arranged outsidethe image pickup section (light receiving section) 30 a, and an outputsection 36 is connected to the horizontal transfer registers 34.

Four types of horizontally extending vertical transfer electrodes 32(ended with suffix numbers _1, _2, _3, and _4) are arranged in avertical direction with a predetermined order in a manner such that anopening is provided on the light receiving surface of the lightreceiving sensors 31. The vertical transfer electrodes 32 are arrangedon the vertical transfer registers 33 (light receiving surfaces)extending in the (vertical) direction of columns so that the verticaltransfer registers 33 at the same vertical position at each column aregrouped.

The four types of vertical transfer electrodes 32 are mounted so thattwo vertical transfer electrodes 32 correspond to a single lightreceiving sensor 31. The vertical transfer electrodes 32 are driven totransfer charge in the vertical direction by four types of verticaltransfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4 supplied from the drivingcircuit 4. Every two light receiving sensors 31 (except the final stagethereof on the side of the horizontal transfer registers 34) are pairedin one set. The four vertical transfer electrodes 32 are thus suppliedwith the vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4respectively by the driving circuit 4.

As shown, on the side of the horizontal transfer registers 34, verticaltransfer electrodes 32 are arranged for a set of four vertical transferregisters 33. The uppermost vertical transfer register 33 among the setcorresponds to the vertical transfer electrode 32_1 supplied with thevertical transfer pulse ΦV_1. The one stage preceding vertical transferelectrode 32_2 (closer to the horizontal transfer registers 34) isprovided with the vertical transfer pulse ΦV_2. The one stage precedingvertical transfer electrode 32_3 (closer to the horizontal transferregisters 34) is provided with the vertical transfer pulse ΦV_3. Thevertical transfer electrode 32_4 closest to the horizontal transferregisters 34 is provided with the vertical transfer pulse ΦV_4.

The vertical transfer registers 33 are connected to the horizontaltransfer register 34 via the one set of vertical transfer electrodes 32at the last stage, namely 32_1 through 32_4 (supplied with ΦV_1 throughΦ_4).

As for the horizontal transfer registers 34, two horizontal transferelectrodes 35 (ended with suffixes _1 and _2) are arranged for a singlevertical transfer register 33. The horizontal transfer electrodes 35 aresupplied with two phase horizontal driving pulses ΦH_1 and ΦH_2 from thedriving circuit 4 to horizontally transfer signal charge.

In the CCD solid-state image pickup element 30 thus constructed, thelight receiving sensors 31 photoelectrically converts received light,and stores signal charge responsive to an amount of received light. Thesignal charge of the light receiving sensor 31 is read into the verticaltransfer register 33 during a vertical blanking period. Signal charge ofone horizontal line is vertically transferred every horizontal blankingperiod. As a result, a so-called vertical line shift is performed totransfer the signal charge to the horizontal transfer registers 34. Thesignal charge transferred to the horizontal transfer registers 34 ishorizontally transferred during an effective horizontal transfer period,and then output to the outside via the output section 36.

The vertical line shift of the signal charge in the known CCDsolid-state image pickup element 30 is designed to be performed inresponse to the vertical transfer pulses (ΦV_1 through ΦV_4) during thehorizontal blanking period Hb of television as represented by drivingtiming of a vertical line shift of FIG. 25B. More specifically, as shownin FIG. 25B, in the vertical line shifting of signal charge, the signalcharge staying on the vertical transfer electrodes 32_2 and 32_3corresponding to ΦV_2 and ΦV_3 is shifted to the horizontal transferregisters 34 in response to the four vertical transfer pulses ΦV_1,ΦV_2, ΦV_3, and ΦV_4 during the horizontal blanking period Hb. Morespecifically, at the falling edge of the vertical driving pulse ΦV_4 ofthe vertical transfer electrode 32_4, the signal charge is transferredto the horizontal transfer electrode 35_1 supplied with the horizontaldriving pulse ΦH_1 of the horizontal transfer registers 34.

In the vertical line shifting, a gradient ΔV/ΔT of the rising edge andthe falling edge of the vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, andΦV_4 respectively applied to the vertical transfer electrodes 32_1through 32_4 (ΔV represent voltage and ΔT represents time) during thehorizontal blanking period Hb, namely, a transient speed (ΔV/ΔT) equalsthe transient speed (ΔV/ΔT) of the vertical transfer pulses ΦV_1, ΦV_2,ΦV_3, and ΦV_4 respectively applied to the vertical transfer electrodes32_1 through 32_4 during the vertical blanking period. FIG. 25Billustrates the driving pulse as a rectangular pulse having a verticallyrising edge and a vertically falling edge.

High-speed vertical transfer is required during the vertical blankingperiod in the electronic image stabilization operation in the imagepickup device such as a video camera using the CCD solid-state imagepickup element, or in the CCD solid-state image pickup element of frameinterline transfer (FIT) system applied for broadcasting business.

Japanese Unexamined Patent Application Publication No. 2000-138943 hasproposed a technique in which a CCD solid-state image pickup elementperforms vertical line shifting with four types of vertical transferpulses during the horizontal blanking period.

In the CCD solid-state image pickup element 30, the vertical line shiftand the high-speed vertical transfer are driven by vertical drivescanning circuits of the same characteristic, namely, a vertical driverin the driving circuit 4. A complementary metal oxide semiconductor(CMOS) type vertical driver featuring high speed is typically used. Ifthe vertical transfer is performed during the effective horizontalscanning period, noise due to crosstalk in the CCD solid-state imagepickup element 30 (coupling noise) occurs at the moment the verticaltransfer pulses (ΦV_1 through ΦV_4) are applied.

More specifically, cross-talk noise is induced on a CCD output signal,appearing as vertical streak noise because the transient speed at therising edge and the falling edge of the driving waveform is high,namely, the gradient ΔV/ΔT of the rising edge and the falling edge ofthe vertical transfer pulses (ΦV_1 through ΦV_4) is large when thevertical transfer is performed during the horizontal scanning period. Inother words, image quality is degraded (with noise) in response to hightransient speed in the driving waveform. Further discussion about thiswill be provided in connection with embodiments of the presentinvention. One reason for the image degradation is that transientvariations of a driving voltage on one electrode interferes with adriving voltage on another electrode.

To prevent image degradation, the vertical driving (vertical transfer)is performed outside the effective horizontal scanning period in theknown art. More specifically, if the application of the verticaltransfer pulses (ΦV_1 through ΦV_4) is performed during the horizontalblanking period, no problem is caused in image when the vertical lineshift is performed. In the known CCD solid-state image pickup element,the vertical transfer for vertical line shifting is performed during thehorizontal blanking period.

When TV method was typical, the horizontal blanking period was definedby the TV method, and it was sufficient if the vertical line shiftingwas performed during the horizontal blanking period. However, if themulti-pixel design and high-frame rate design are incorporatedregardless of the TV method, the horizontal blanking period for thevertical line shifting becomes useless, and presents difficulty in thepromotion of high frame-rate design.

To incorporate high frame rate design, the horizontal blanking periodneeds to be shortened. To this end, the vertical line shifting needs tobe performed at high speed. To perform the vertical line shifting athigh speed, a transfer electrode needs to have a low resistance. As oneway to achieve low resistance, widening an electrode area iscontemplated. It is difficult to widen the transfer electrode inhorizontal direction. The thickness of the transfer electrode needs tobe increased. If the thickness of the transfer electrode is increasedtoo much, the height of a step around a sensor aperture becomes toolarge. When light enters, obliquely entering light is blocked, leadingto drop in sensitivity and generation of shading. It is thus difficultto increase vertical transfer speed.

Even if an output rate of signal is increased to achieve a high framerate in an electronic apparatus such as a digital still camera employinga CCD solid-state image pickup element not compatible with TV method,the horizontal blanking period becomes long. It is thus difficult toincrease the output rate above a predetermined value.

Japanese Unexamined Patent Application Publication No. 2005-269060assigned to the same assignee of this invention discloses a mechanismthat achieves a high frame rate by substantially shortening a horizontalblanking period.

In the disclosed mechanism, a driving clock waveform having a transientspeed ΔV/ΔT as a rising edge and a falling edge (ΔV represents voltageand ΔT represents time), i.e., a pulse signal being smooth and mild ingradient is supplied as a transfer pulse to a transfer electrode as acapacitive reactance. In high-density CCD, vertical transfer performedduring an effective pixel period leads to a high frame rate with a slowclock rate. To this end, a smooth and mildly inclined gradient pulsesignal is required.

SUMMARY OF THE INVENTION

It is thus desirable to provide a mechanism that permits high-speedreading of signal with noise generation due to interference betweendriving voltages controlled when a capacitive load such as a CCDsolid-state image pickup element is driven by at least two drivingvoltages.

Driving the capacitive load with a constant current is contemplated asdisclosed in Japanese Unexamined Patent Application Publication No.2005-269060 in order to keep the gradient of the driving pulse asconstant as possible when the capacitive load is driven with a smoothand mildly inclined gradient pulse signal (voltage pulse in this case).However, constant current driving, if merely used, is subject tovariations in the manufacture of load capacitance and variations in themanufacture of a driving device, and environmental variations, andappropriate driving may not be performed. If phase relationship isshifted due to variations in the manufacture of load capacitance andvariations in the manufacture of a driving device, appropriate drivingmay not be performed. This problem will also be further described laterin the discussion of embodiments of the present invention.

The problem is also possible if an inductive reactance as opposed to thecapacitive reactance is used. Driving the inductive load with a constantvoltage is contemplated in order to keep the gradient of the drivingpulse as constant as possible when the inductive load is driven with asmooth and mildly inclined gradient pulse signal (current pulse in thiscase). However, constant voltage driving, if merely used, is subject tovariations in the manufacture of load capacitance and variations in themanufacture of a driving device, and environmental variations, andappropriate driving may not be performed. If phase relationship isshifted due to variations in the manufacture of load inductance andvariations in the manufacture of a driving device, appropriate drivingmay not be performed.

It is thus desirable to provide a mechanism that reduces drivingperformance drop due to operational variations and environmentalvariations when the load is driven with a pulse having mild transientcharacteristic.

In one embodiment of the present invention, a semiconductor deviceincludes charge generating sections arranged in a matrix for generatingsignal charge responsive to an input electromagnetic wave, a firstcharge transfer section for successively transferring in one directionthe signal charge generated by the charge generating section, and asecond charge transfer section for successively transferring the signalcharge, transferred by the first charge transfer section, in anotherdirection different from the one direction, and a charge storage sectionarranged between the first charge transfer section and the second chargetransfer section.

Here, the “one direction” and the “other direction” are relative to eachother. Generally, the one direction corresponds to a direction ofcolumns or a vertical direction for low speed scanning and the otherdirection corresponds to a direction of rows or a horizontal directionfor high speed scanning. For example, if the screen is rotated by 90degrees, up and down and left and right relationship changes, and rowand column or vertical to horizontal relationship also changes. Therelationship is not absolute. For example, if the first charge transfersection is in the direction of columns, the second charge transfersection is in the direction of rows, and if the second charge transfersection is in the direction of columns, the first charge transfersection is in the direction of rows. Hereinafter, the one direction isrepresented by the direction of columns or the vertical direction, andthe other direction is represented by the direction of rows or thehorizontal direction.

A signal charge of a predetermined unit (typically of one row) of therow direction generated by the charge generating sections is transferredto the charge storage section by driving the transfer in the columndirection within an effective transfer period of the row direction, andthe signal charge of the row direction transferred to the charge storagesection of a predetermined unit (typically of one row) is transferred tothe second charge transfer section by driving the signal charge outsidethe effective transfer period of the row direction.

In one embodiment of the present invention, the driving in the rowdirection within the effective transfer period is performed with thedriving signals that are alternately reverse-phased every set of drivingsignals, namely, at least every two driving signals. With the twodriving signals reversed, noise components arising from the drivingsignals are also reverse-phased, thereby canceling each other.

In one embodiment of the present invention, the driving in the rowdirection within the effective transfer period allows a noise correctionsignal reverse-phased from noise on the semiconductor substrate to besupplied to a predetermined location of the semiconductor substrate. Thereverse-phased correction signal is thus positively supplied to reducesubstrate noise arising from the driving signal.

In one embodiment of the present invention, the driving signal issupplied to the semiconductor device via a noise control circuit. Thenoise control circuit for controlling the noise on a driving signal lineis arranged in the driving signal line between a driver circuit and thesemiconductor device.

In one embodiment of the present invention, a capacitive functionalelement is provided to make a grounding resistance of the semiconductorsubstrate capacitive. As will be described in detail later, a noisesource of the substrate noise is found to be the resistance of thesubstrate. A driving current responsive to a driving signal flowsthrough the substrate resistance. By allowing the driving current toflow through the capacitive functional element, the substrate noise maybe reduced.

In one embodiment of the present invention, a waveform shaping processorperforms a predetermined waveform shaping process on an input pulsesignal to drive a load with the input pulse. A drive pulse waveformshaping controller monitors a pulse output signal caused in the load andcontrols an adjustment value of the waveform shaping processor so thattransient characteristics of the pulse output signal, such as a delayamount and variation characteristic, become predeterminedcharacteristics.

The pulse output signal actively caused in the load is feed-backcontrolled so that the pulse output signal has predetermined transientcharacteristics.

In accordance with embodiments of the present invention, during thecharge transfer in the column direction, the reverse-phased drivingsignals are used. The noise correction signal opposite in phase to thesubstrate noise is supplied to the substrate. The driving signal issupplied via the noise control circuit. The substrate groundingresistance is made capacitive. Cross-talk noise generated during thecharge transfer in the column direction is thus reduced.

A combination of the above-described embodiments reduces even more thecross-talk noise during the charge transfer.

With the active pulse output signal monitored, the feedback control isperformed so that the pulse output signal has predetermined transientcharacteristic. Constant transient characteristics are thus obtainedeven if the semiconductor suffers from load characteristic variationsfrom load to load, driving characteristic variations from element toelement, and environmental variations.

The load is driven by the pulse signal having the mild transientcharacteristics with continuously appropriate phase delay and gradientcharacteristic in a manner from variations in the manufacture of loadcapacitance and variations in the manufacture of a driving device andenvironmental variations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image pickup device as one example of anelectronic apparatus in accordance with one embodiment of the presentinvention;

FIG. 2 illustrates a layout example of four types of vertical transferelectrodes of a CCD solid-state image pickup element of FIG. 1;

FIGS. 3A-3C illustrate a layout model of a vertical transfer electrodeof a CCD solid-state image pickup element of FIG. 1, a semiconductorsubstrate SUB and an output amplifier;

FIGS. 4A-4C illustrate the relationship between an equivalent circuit ofa vertical driver and the CCD solid-state image pickup element;

FIGS. 5A1-5B2 illustrate a step response of a vertical transfer pulseΦV;

FIGS. 6A and 6B are timing diagrams illustrating a driving timing of theCCD solid-state image pickup element of FIG. 1 in accordance with afirst embodiment of the present invention;

FIGS. 7A and 7B are timing diagrams illustrating a driving timing of theCCD solid-state image pickup element, not driven in a complementarydriving method, in accordance with the first embodiment of the presentinvention;

FIGS. 8A-8C illustrate the relationship between an equivalent circuit ofthe vertical driver and the CCD solid-state image pickup element;

FIGS. 9A and 9B illustrate the principle in which the vertical driverreduces transient speed;

FIG. 10 illustrates an additional advantage provided by complementarydriving;

FIG. 11 is a first timing chart illustrating one driving timing;

FIG. 12 is a second timing chart illustrating another driving timing;

FIG. 13 is a third timing chart illustrating yet one driving timing;

FIG. 14 is a fourth timing chart illustrating a further driving timing;

FIG. 15 is a fifth timing chart illustrating a further driving timing;

FIG. 16 is a sixth timing chart illustrating a further driving timing;

FIG. 17 is a seventh timing chart illustrating a further driving timing;

FIG. 18 is an eighth timing chart illustrating a further driving timing;

FIG. 19 illustrates a noise control method in accordance with a secondembodiment of the present invention;

FIGS. 20A-20E illustrate a noise control method in accordance with athird embodiment of the present invention;

FIGS. 21A and 21B illustrate a noise control method in accordance with afourth embodiment of the present invention;

FIGS. 22A and 22B illustrate a mechanism of a known image pickup device;

FIG. 23 generally illustrates a pulse driver having a feedback controlshaping function for a drive pulse waveform;

FIGS. 24A and 24B are timing diagrams illustrating operation of thepulse driver of FIG. 23;

FIGS. 25A and 25B are timing diagrams illustrating the operation of thepulse driver of FIG. 23, particularly, gradient characteristic duringtransition;

FIG. 26 illustrates in detail the pulse driver of FIG. 23 driving acapacitive reactance load;

FIG. 27 is a timing diagram illustrating the operation of the pulsedriver of FIG. 26;

FIG. 28 illustrates in detail the pulse driver of FIG. 23 driving aninductive reactance load;

FIG. 29 is a timing diagram illustrating the operation of the pulsedriver of FIG. 28;

FIG. 30 illustrates in detail a phase delay adjuster and a through rateadjuster in the pulse driver of FIG. 23;

FIG. 31 is a timing diagram of the operation of the pulse driver of FIG.30;

FIG. 32 illustrates in detail another example of the phase delayadjuster and the through rate adjuster in the pulse driver of FIG. 23(modification to the arrangement shown in FIG. 17);

FIG. 33 illustrates in detail the a drive pulse waveform shapingcontroller in the pulse driver of FIG. 23;

FIGS. 34A-34C are timing diagrams illustrating the operation of thepulse driver of FIG. 33;

FIG. 35 illustrates a first configuration of a vertical driverimplementing the pulse driver;

FIG. 36 illustrates a second configuration of the vertical driverimplementing the pulse driver;

FIG. 37 illustrates a third configuration of the vertical driverimplementing the pulse driver;

FIG. 38 illustrates a fourth configuration of the vertical driverimplementing the pulse driver; and

FIGS. 39A and 39B illustrate a mechanism of a known image pickup device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention are described below withreference to the drawings.

Referring to the drawings, there are shown image pickup devices 1 and 3,drive controller (driving circuit) 5, vertical transfer driver 7,horizontal transfer driver 8, CCD solid-state image pickup elements 10and 30, image pickup section 10 a, photo-receiving sensor 11, verticaltransfer electrode 12, vertical transfer register 13, horizontaltransfer register 14, output amplifier 16, correlated double samplingcircuit 17, noise correction signal supply circuit 200, storage gateelectrode 21, phase inverting circuit 210, hold gate electrode 22,waveform shaping circuit 220, capacitor 222, resistor 224, read-out gate23, embedded channel section 24, gate insulating layer 25, image pickupsection 30 a, photo-receiving sensor 31, vertical drivers 40 and 50,sensor aperture 118, light shielding layer 119, transistor 120,electrode 121, VSUB terminal 130, and PWELL ground terminals 131 and132. Also shown are noise control circuit 310, capacitor 316, verticaltransfer electrode 32, resistor 322, vertical transfer transistor 33,inductance 334, horizontal transfer register 34, inductance 344,horizontal transfer electrode 35, output section 36, driver circuit 4,capacitor 412, vertical driver 50, inverter 51, level shift circuits 52and 53, voltage output section 54, impedance controller 55, delay lines56 and 57, switches 58 and 59, CCD solid-state image pickup elements 60and 80, coupling capacitors C1, C2, and C3, resistor Ro, light shieldingresistor R1, equivalent resistance of the light shielding layer R10,protective resistor R12, substrate resistor R2, and grounding resistorsR61 and R81. Also shown are storage gate section STG, output impedanceZo, impedance element Z58, read-out gate section ROG, pulse driver 600,load 609, phase delay adjuster 610, pulse delay circuit 612, delay clockcount register 614, through rate adjuster 630, current output section632, voltage output section 633, and digital-to-analog (D/A) converter634. Also shown are switch 636, DAC data register 638, load driver 650,current mirror circuit 652, constant voltage output circuit 653,junction point (current addition point) 656, voltage adder 657, loadcurrent detector 658, waveform shaping processor 660, drive pulsewaveform shaping controller 670, phase delay controller 672, and throughrate controller 674. Also shown are comparators 682 and 684, voltagecomparators 682A and 684A, counters 682B and 684B, determiner 686,vertical driver 700, switch 708, phase delay adjuster 710, through rateadjuster 730, current distributor 740, load driver 750, waveform shapingprocessor 760, drive pulse waveform shaping controller 770, phase delaycontroller 772, through rate controller 774, operation controller 790,timing signal generator 810, analog front-end section 820, video signalprocessor 830, video calculation and processing unit 832, video recorder834, video display 836, switches 852, 854 and 856, and selection signalgenerator 860.

General Construction of Image Pickup Device

FIG. 1 illustrates an image pickup device 1 as one example of electronicapparatus in accordance with one embodiment of the present invention.The image pickup device 1 employs a CCD solid-state image pickup element10 of interline transfer (IT) system.

The IT CCD solid-state image pickup element 10 includes a twodimensional matrix of a large number of photo cells (light receivingsections), a plurality of vertical transfer CCDs ΦV registers) betweenvertical columns of photo cells, and horizontal transfer CCDs next tothe final row of vertical transfer CCDs. The image pickup device 1 isdescribed in detail below.

As shown in FIG. 1, the image pickup device 1 of the present embodimentincludes the IT CCD solid-state image pickup element 10 and a drivingcircuit 5 as a driving device for driving the IT CCD solid-state imagepickup element 10.

The CCD solid-state image pickup element 10 includes an image pickupsection 10 a. The image pickup section 10 a includes a two dimensionalmatrix of photo sensors (charge generating section) 11 serving aspixels, and vertical transfer registers (an example of vertical transfersections) 13 having a CCD structure and vertically extendingcorresponding to the photo sensors 11. The photo sensors 11 convertslight incident thereon into a signal charge responsive to an amount ofincident light and stores the charge.

The image pickup section 10 a further includes read-out gates (ROG) 18,each between the vertical transfer register 13 and the photo sensor 11,and a channel stop ST 19 on the border of each pixel (unit cell).

The CCD solid-state image pickup element 10 of the present embodimentincludes, as a feature thereof, a charge storage section 10 b, arrangedoutside the image pickup section 10 a, for temporarily storing a signalcharge vertically transferred from the image pickup section 10 a. Ahorizontal transfer register 14 having the CCD structure (one example ofthe second charge transfer section) is arranged to be connected to thecharge storage section 10 b. A substantial difference between the CCDsolid-state image pickup element 10 and the CCD solid-state image pickupelement 30 of FIG. 22 is that the CCD solid-state image pickup element10 includes the charge storage section 10 b between the image pickupsection 10 a and the horizontal transfer register 14.

Like the image pickup section 10 a, the charge storage section 10 bincludes a vertical transfer register 13 having a CCD structure. Thevertical transfer register 13 is arranged in a dual structure. A portionof the image pickup section 10 a containing part of the verticaltransfer register 13 is referred to as a storage gate section STG and aportion of the horizontal transfer register 14 containing part of thevertical transfer register 13 is referred to as a hold gate section HLG.

One line of the horizontal transfer registers 14 having the CCDstructure extending from left to right in FIG. 1 is connected to thefinal row of each of the vertical transfer register 13 of the chargestorage section 10 b (i.e., hold gate section HLG). The output end ofthe horizontal transfer register 14 connects to an output amplifier 16as a charge detector (or output unit) for converting the signal chargeinto an electrical signal (typically a voltage signal), and the outputend of the output amplifier 16 connects to a correlated double sample(CDS) circuit 17.

The CCD solid-state image pickup element 10 herein includes the CDScircuit 17. Alternatively, the CDS circuit 17 may be arranged externalto the CCD solid-state image pickup element 10.

The output amplifier 16 accumulates, onto a floating diffusion, thesignal charge successively entered from the horizontal transferregisters 14, converts the accumulated signal charge into a signalvoltage, and then outputs the converted signal voltage to the CDScircuit 17 as a CCD output signal via an output circuit composed of asource-follower transistor circuit (not shown). The correlated doublesampling circuit 17 restricts a noise component such as reset noisecontained in the CCD output signal and outputs the resulting CCD outputsignal as an image signal Sout from an output terminal tout.

Four types of vertical transfer electrodes 12 (ending with suffixes _1,_2, _3, and _4) are arranged on the vertical transfer registers 13 (onthe light receiving side) at the same vertical positions of the verticaltransfer registers 13 at a predetermined order in the vertical directionso that the aperture of the light receiving surface of the photo sensor11 (as shown in FIGS. 2 and 3A-3C) is formed. The vertical transferelectrodes 12 extend horizontally across the image pickup device 1 toform the aperture on the light receiving side of the photo sensor 11.

The four types of vertical transfer electrodes 12 are arranged so thattwo vertical transfer electrodes 12 correspond to a single photo sensor11. Four vertical transfer pulses ΦV_1, ΦV_2, ΦV_3 and ΦV_4 suppliedfrom the driving circuit 5 transfer the signal charge in the verticaldirection. More specifically, every two photo sensors 11 are paired as aset (including the last stage of the charge storage section 10 b), andfour vertical transfer electrodes 12 are supplied with the verticaltransfer pulses ΦV_1, ΦV_2, ΦV_3 and ΦV_4, respectively.

As shown in FIG. 1, the vertical transfer electrodes 12 are arranged foreach set of four vertical transfer registers 13 in the verticaldirection. The vertically topmost photo sensor 11 corresponds to avertical transfer electrode 12_1 supplied with the vertical transferpulse ΦV_1. The one stage preceding vertical transfer electrode 12_2(closer to the charge storage section 10 b) is supplied with thevertical transfer pulse ΦV_2. The further one stage preceding verticaltransfer electrode 12_3 (closer to the charge storage section 10 b) issupplied with the vertical transfer pulse ΦV_3. The vertical transferelectrode 12_4 closest to the charge storage section 10 b is suppliedwith the vertical transfer pulse ΦV_4.

The vertical transfer register 13 is connected to the subsequentvertical transfer register 13 of the charge storage section 10 b via thefinal set of vertical transfer electrodes 12 (transfer electrodessupplied with the vertical transfer pulses ΦV_1 through ΦV_4), namely,12_1 through 12_4. Two types of the transfer electrodes, including thestorage gate electrode 21 and the hold gate electrode 22, are arrangedon the charge storage section 10 b (on the same light receiving surfaceof the image pickup section 10 a) common to the vertical transferregisters 13 at the same vertical position. The storage gate electrodes21 and the hold gate electrodes 22 are arranged horizontally across theimage pickup device 1.

The storage gate electrode 21 and the hold gate electrode 22 arearranged on the output end of the vertical transfer electrode 12_4(supplied with the vertical transfer pulse ΦV_4) formed on the verticaltransfer register 13 as the output end of the image pickup section 10 a.The driving circuit 5 supplies the storage gate electrode 21 with astorage gate pulse ΦVSTC and the hold gate electrode 22 with a hold gatepulse ΦVHLG.

Each horizontal transfer register 14 is arranged for two horizontaltransfer electrodes 15 (ending with suffixes _1 and _2) for eachvertical transfer register 13. The horizontal transfer registers 14transfer horizontally the signal charge with two phase horizontaldriving pulses ΦH_1 and ΦH_2.

The operation of the image pickup device 1 is summarized as below. Whenread-out pulse XSG (ΦROG) issued from the driving circuit 5 is appliedto a gate electrode of read-out gate ORG 18 making the potential of thegate electrode deep, the signal charge accumulated in each of the photosensors 11 of the CCD solid-state image pickup element 10 is read to thevertical transfer register 13 via the read-out gate ROG. The reading ofthe signal charge from the photo sensor 11 to the vertical transferregister 13 is particularly referred to as field shift.

The vertical transfer registers 13 of the image pickup section 10 a aretransfer driven by the four vertical transfer pulses ΦV_1 through ΦV_4corresponding to the four vertical transfer electrodes 12. A storagegate section STG of the charge storage section 10 b is driven by astorage gate pulse ΦVSTG and a hold gate section HLG is driven by a holdgate pulse ΦVHLG. In this way, the signal charge read from the photosensor 11 is vertically transferred with one scanning line at a time,and then transferred to the horizontal transfer registers 14.

Unlike the image pickup section 10 a, the charge storage section 10 bcomposed of the storage gate section STG and the hold gate section HLGcan be designed regardless of vertical pixel pitch. The electrode widthof each of the storage gate electrode 21 and the hold gate electrode 22can be increased in order to introduce low resistance design in thestorage gate electrode 21 and the hold gate electrode 22. This isparticularly advantageous in the high speed vertical charge transferfrom the charge storage section 10 b to the horizontal transferregisters 14.

As will be described in detail later, the vertical charge transfer(i.e., vertical line shift) is different from a vertical line shifttypically performed during part of the normal horizontal blankingperiod. The vertical line shift in the image pickup section 10 a isperformed during a portion of the effectively horizontal period, and thevertical line shift in the charge storage section 10 b is performedduring a portion of the horizontal blanking period.

In response to the two-phase horizontal transfer pulses ΦH_1 and ΦH_2issued from the driving circuit 5, the horizontal transfer registers 14horizontally transfer, to the output amplifier 16, the signal charge ofone line vertically transferred from the plurality of vertical transferregisters 13.

The output amplifier 16 converts the signal charge successively inputfrom the horizontal transfer register 14 into a signal voltage, andsupplies the signal voltage as a CCD output signal to the correlateddouble sampling circuit 17. The correlated double sampling circuit 17restricts a noise component contained in the CCD output signal and thenoutputs the resulting CCD output signal as an image signal Sout to theoutside from an output terminal tout.

Layout Structure of Vertical Transfer Electrode

FIG. 2 illustrates an example of layout structure of four types verticaltransfer electrodes 12 of the CCD solid-state image pickup element 10 ofFIG. 1.

As shown in FIG. 2, a plurality of vertical transfer registers ΦV-CCD)13 are arranged between the vertical lines of a two-dimensional matrixof photo sensors 11, and the read-out gate section ROG 18 is interposedbetween the photo sensor 11 and the vertical transfer register 13. Achannel stop section CS 19 is arranged on the border of each pixel (unitcell).

The four types of vertical transfer electrodes 12 fabricated ofpolysilicon thin film extending horizontally are arranged on the lightreceiving surface of the vertical transfer registers 13 (on the frontside of the sheet of the drawing) to be common with the verticaltransfer registers 13 at the same vertical position in each column. Asensor aperture 118 is left on the light receiving surface of the photosensor 11.

The layout structure herein permits two-layer and four-phase driving.Arranged on first layer vertical transfer electrodes 12_2 and 12_4respectively supplied with the vertical transfer pulses ΦV_2 and ΦV_4are second layer vertical transfer electrodes 12_1 and 12_3 respectivelysupplied with the vertical transfer pulses ΦV_1 and ΦV_3.

In each layer, the patterns of the vertical transfer electrodes 12 aresubstantially identical to each other. As shown, the first layervertical transfer electrode (second electrode) 12_2 and the first layervertical transfer electrode (fourth electrode) 12_4 are identical inpattern to each other, and the second layer vertical transfer electrode(first electrode) 12_1 and the second layer vertical transfer electrode(third electrode) 12_3 are identical in pattern to each other. Thevertical transfer electrode 12_1 and the vertical transfer electrode12_2 overlap each other in a two-layer structure and the verticaltransfer electrode 12_3 and the vertical transfer electrode 12_4 overlapeach other in a two-layer structure. The first layer and the secondlayer are different in pattern.

The four types of vertical transfer electrodes 12 cover the majorportion of the image pickup section 10 a of the CCD solid-state imagepickup element 10, and are arranged in the two-layer structure,presenting a large overlapping capacitance between electrodes.

Structure and Equivalent Circuit

FIGS. 3A-3C illustrate a layout model of the vertical transferelectrodes 12 of the CCD solid-state image pickup element 10 of FIG. 1,a semiconductor substrate SUB (first semiconductor substrate), and theoutput amplifier 16. FIG. 3A is a plan view of one photo sensor 11, FIG.3B is plan view of a MOS transistor portion formed in the outputamplifier 16, and FIG. 3C is a sectional view of the MOS transistorportion in FIG. 3B.

In the image pickup section 10 a, PWELL-#2 a (an example of secondsemiconductor substrate) is formed on the surface of the siliconsemiconductor substrate NSUB. Arranged on the PWELL-2 a are the photosensor 11, fabricated of a PN junction photo diode, the read-out gatesection ROG, PWELL-#1, the vertical transfer register 13 formed on thePWELL-#1 (represented by V register BC), and the channel stop section CSin that order on the left-hand side in the right to left direction. Thesubstrate structure is identical to the IT-CCD structure.

Arranged on these elements are dielectric layer (not shown), on whichthe vertical transfer electrodes 12 (12_1 or 12_3) for the verticaltransfer registers 13 are arranged to form the sensor aperture 118. Alight shielding layer 119 is formed on a dielectric layer (not shown) onthe vertical transfer electrodes 12 in a manner such that the sensoraperture 118 is formed above the photo sensor 11. The vertical transferelectrode 12 is supplied with one of the four types of vertical transferpulses (ΦV_1 or ΦV_3).

The vertical transfer electrodes 12 and the light shielding layer 119generally covering the CCD solid-state image pickup element 10 aredefined by the sensor aperture 118 on the photo sensor 11. Through thesensor aperture 118, light is incident on the photo sensor 11.

In the output amplifier 16, PWELL-#2 b (one example of the secondsemiconductor substrate) is formed on the silicon semiconductorsubstrate NSUB as in the image pickup section 10 a. A transistor 120 isformed on the PWELL-#2 b. Arranged further on the transistor 120 is anelectrode 121 with a dielectric layer (not shown) interposedtherebetween.

A VSUB terminal 130 of the semiconductor substrate NSUB, a terminal 131of the PWELL-#2 a, and a terminal 132 of the PWELL-#2 b shown in thesectional view of FIG. 3C are supplied with a standard DC bias Vbias. Asshown, the VSUB terminal 130 is supplied with the DC bias Vbias, and theterminals 131 and 132 of the PWELL-#2 a and the PWELL-#2 b are grounded.The terminals 131 and 132 may also be referred to PWELL ground terminals131 and 132.

As shown in FIG. 3C, a coupling capacitor C1 is formed between thevertical transfer electrode 12 and the light shielding layer 119 and acoupling capacitor C2 is formed between the vertical transfer electrode12 and the semiconductor substrate NSUB in the image pickup section 10a. On the side of the output amplifier 16, a coupling capacitor C3 isformed between the gate of the transistor 120 and the semiconductorsubstrate NSUB because of the back gate effect.

An equivalent capacitor CL between each vertical transfer electrode 12and the CCD substrate is considered to be approximately equal to theparallel component of the coupling capacitors C1 and C2. Capacitorsrelated to the vertical transfer electrodes 12 are an electrodecapacitor with the other vertical transfer electrodes 12 (see C64 ofFIGS. 4A and 8A) besides the coupling capacitors C1 and C2.

Grounding resistance present in the CCD solid-state image pickup element10 includes a light shielding layer resistor R1 created between thelight shielding layer 119 and the ground GND, and a substrate resistorR2 of the semiconductor substrate NSUB. The overall grounding resistanceR is considered to be approximately equal to a parallel component of thelight shielding layer resistor R1 and the substrate resistor R2.

As for resistance between the light shielding layer 119 and the groundGND, the light shielding layer resistor R1 includes, in addition to anequivalent resistance R10 of the light shielding layer 119, a protectiveresistor R12 of several hundred Ω to several tens of kilo Ωintentionally added to prevent electrostatic breakdown. Since theprotective resistor R12 is grounded via a terminal 133, the equivalentresistor R10 of the light shielding layer 119 is on the side of thelight shielding layer 119 rather than on the side of the terminal 133.The entire light shielding layer resistor R1 is a parallel component ofthe equivalent resistor R10 of the light shielding layer 119 and theprotective resistor R12. Since the resistance value of the protectiveresistor R12 is larger than the resistance value of the equivalentresistor R10 of the light shielding layer 119, the grounding resistanceR is defined with the substrate resistor R2 predominant.

As understood from not only FIG. 2 but also from FIGS. 3A-3C, the fourtypes of vertical transfer electrodes 12 generally cover the imagepickup section 10 a of the CCD solid-state image pickup element 10. Forthis reason, the substrate voltage fluctuates in response to thevertical transfer pulse ΦV supplied to the vertical transfer electrodes12. In other words, noise Noise1 is created on the semiconductorsubstrate NSUB. The noise Noise1 is then coupled to the transistor 120via the coupling capacitor C3 because of the back gate effect to thetransistor 120 forming the output amplifier 16 on the substrate. As aresult, the noise is superimposed on the output signal, creatingvertical streak noise.

The vertical transfer electrode 12 is capacitively coupled to the lightshielding layer 119 via the coupling capacitor C1 and to thesemiconductor substrate NSUB via the coupling capacitor C2. The lightshielding layer 119 is grounded to the ground GND via the lightshielding layer resistor R1. The ground GND is connected to the PWELL-#2b of the output amplifier 16 via the PWELL ground terminal 132.

Noise Noise2 arising from the vertical transfer pulse ΦV supplied to thevertical transfer electrode 12 fluctuates the PWELL-#2 b of the outputamplifier 16 via the coupling capacitor C1, the light shielding layer119, the light shielding layer resistor R1, and the ground GND. With theback gate effect to the transistor 120 forming the output amplifier 16,the noise Noise2 is induced on the transistor 120, and superimposed onthe output signal, thereby becoming vertical streak noise.

How to control the fluctuation of the semiconductor substrate NSUB andthe fluctuation of the PWELL-#2 b of the output amplifier 16 isimportant in noise control.

Analysis of Noise Generation Mechanism

FIGS. 4A-4C and FIGS. 5A1-5B2 illustrate a streak noise generationmechanism from the standpoint of circuit analysis. FIGS. 4A-4Cillustrate the relationship between the equivalent circuit of thevertical driver and the CCD solid-state image pickup element 30. FIG.5A1-5B2 illustrate a step response of the vertical transfer pulse ΦV.

On the side of the image pickup section 10 a, a coupling capacitor C1 iscreated between a vertical transfer electrode 32 and a light shieldinglayer, and a coupling capacitor C2 is created between the verticaltransfer electrode 32 and a semiconductor substrate NSUB. On the side ofan output amplifier 36, a coupling capacitor C3 is created between thegate of a transistor forming the output amplifier 36 and thesemiconductor substrate NSUB because of the back gate effect. Theseelements are not shown in FIGS. 4A-4C.

The equivalent capacitor CL between each vertical transfer electrode 32and the CCD substrate is considered to be approximately equal to theparallel component of the coupling capacitor C1 and the couplingcapacitor C2. Capacitance related to the vertical transfer electrode 32includes an electrode capacitance with the other vertical transferelectrodes 32 besides the coupling capacitors C1 and C2.

Grounding resistance present in the CCD solid-state image pickup element30 includes a light shielding layer resistor R1 created between thelight shielding layer 119 and the ground GND, and a substrate resistorR2 of the semiconductor substrate NSUB. The overall grounding resistanceR is considered to be approximately equal to a parallel component of thelight shielding layer resistor R1 and the substrate resistor R2.

As shown in FIG. 4A-4C, the CCD solid-state image pickup element 30 isillustrated as a CCD solid-state image pickup element 60 in theequivalent circuit, driven by the driving circuit 4. The CCD solid-stateimage pickup element 60 in the equivalent circuit includes a groundingresistor 61 as an equivalent resistor of the CCD substrate, whichcorresponds to the grounding resistance R of FIG. 3. The groundingresistor 61 is approximately equal to the parallel component of thelight shielding layer resistor R1 and the substrate resistor R2.Resistors R62 and R63 are electrode resistance of the vertical transferelectrode 32. Capacitors C62 and C63 represent equivalent capacitorsbetween the vertical transfer electrode 12 and the CCD substrate.Capacitor C64 represents an equivalent capacitor between the electrodes.

The capacitors C62 and C63 represent equivalent capacitance createdbetween the vertical transfer electrode 12 and the CCD substrate,corresponding to equivalent capacitance CL between each verticaltransfer electrode 12 and the CCD substrate in FIG. 3, and are equal tothe parallel component of the coupling capacitor C1 and the couplingcapacitor C2. Capacitor C64 represents an equivalent capacitance of theelectrode.

The equivalent capacitance of the electrode in the CCD solid-state imagepickup element varies largely depending on the number of pixels, usedprocess, and layout configuration. Typically, the equivalent capacitanceCL (capacitors C62 and C63) falls within a range of 100 to 1000 pF, andthe grounding resistor R61 is several tens of Ω. Each of the resistorsR62 and R63 falls within a range of several tens to several hundreds ofΩ.

A vertical driver 40 for supplying the vertical transfer electrode 32with the vertical transfer pulse ΦV is arranged in the driving circuit4. The vertical driver 40 generates the vertical transfer pulses ΦV_1through ΦV_4, and the CCD solid-state image pickup element 60 includesvertical transfer electrodes 32_1 through 32_4 respectively suppliedwith the vertical transfer pulses ΦV_1 through ΦV_4.

As shown in FIG. 4A-4C, the vertical driver 40 generates only a singlevertical transfer pulse ΦV (output voltage Vout) for simplification ofexplanation. In practice, the CCD solid-state image pickup element 60 isdriven by a plurality of drivers on a per transfer electrode basis (forexample, by other vertical driver or other horizontal driver 70). Forexample, the vertical drivers 40 of the number corresponding to thenumber of types (phases) of vertical transfer electrodes 32 are arrangedto drive the respective vertical transfer electrodes 32.

As seen from the equivalent circuit of the CCD solid-state image pickupelement 60, the CCD solid-state image pickup element 60 (CCD solid-stateimage pickup element 30) is a capacitive reactance load if viewed fromthe vertical driver 40.

The equivalent electrode capacitance of the CCD solid-state image pickupelement varies largely depending on the number of pixels, used process,and layout configuration. Typically, the equivalent capacitance CL(capacitors C62 and C63) falls within a range of 100 to 1000 pF, and thegrounding resistor R61 is on the order of several tens of Ω. Each of theresistors R62 and R63 falls within a range of several tens to severalhundreds of Ω.

The vertical driver 40 for supplying the vertical transfer electrode 32with the vertical transfer pulse ΦV is arranged in the driving circuit4. The vertical driver 40 generates the vertical transfer pulses ΦV_1through ΦV_4, and the CCD solid-state image pickup element 60 includesvertical transfer electrodes 32_1 through 32_4 respectively suppliedwith the vertical transfer pulses ΦV_1 through ΦV_4. As shown in FIG.4A-4C, the vertical driver 40 generates only a single vertical transferpulse ΦV (output voltage Vout) for simplification of explanation. Inpractice, the CCD solid-state image pickup element 60 is driven by aplurality of drivers on a per transfer electrode basis (for example, byother vertical driver or other horizontal driver 70).

The vertical driver 40 includes an inverter 41 for logically inverting acontrol signal Din input from a terminal 403, a level shift (L/S)circuit 42 for outputting a control signal Vg1 in response to thecontrol signal Din input via the terminal 403, and a level shift circuit43 for outputting a control signal Vg2 in response to the level of thecontrol signal NDin into which the inverter 41 has logically invertedthe control signal Din input via the terminal 43.

The vertical driver 40 includes switches 48 and 49 to receive constantvoltages V1 and V2 (having a voltage value V) from terminals 401 and 402at the back ends of the level shift circuits 42 and 43, and output oneof the constant voltages as an output voltage Vout from an outputterminal 404 to the CCD solid-state image pickup element 60.

The vertical driver 40 thus outputs one of the constant voltages V1 andV2 provided to the terminals 401 and 402 from the output terminal 404 asthe output voltage Vout, and supplies the output voltage Vout to the CCDsolid-state image pickup element 60. The voltage V1 may be at a highlevel and the voltage V2 may be at a low level.

The vertical driver 40 receives the control signal Din from the terminal403 and outputs the control signals Vg1 and Vg2 from the level shiftcircuits 42 and 43 to turn on the switches 48 and 49, respectively. Whenthe switch 48 is turned on, the normal output voltage Vout becomes thevoltage V1. When the switch 49 is turned on, the normal output voltageVout becomes the voltage V2.

The CCD solid-state image pickup element 60, represented in theequivalent circuit thereof, is driven by an electrode 601 in response tothe output voltage Vout of the vertical driver 40. For this reason, thedriving signal is applied to the grounding resistor R61 via thecapacitor 62 as an equivalent capacitance between the electrode 601 andthe CCD substrate. A noise component responsive to the output voltageVout thus appears.

The CCD solid-state image pickup element 60, represented in theequivalent circuit thereof, is further driven by the other verticaldriver or other horizontal driver (hereinafter referred to as driver70). The transient variations in the driving voltage on anotherelectrode 602 interferes with the electrode 601, thereby causing imagedegradation such as cross-talk noise.

The driving signal on the other electrode 602 is applied to thegrounding resistor R61, representing the equivalent resistance of theCCD substrate approximately equal to the parallel component of the lightshielding layer resistor R1 and the substrate resistor R2, via thecapacitor 63 as the equivalent capacitance present between the electrode602 and the CCD substrate. The driving signal on the other electrode 602appears on the electrode 601 via the capacitor C64 as the equivalentinter-electrode capacitance, and is then applied to the groundingresistor R61 via the capacitor C63 as the equivalent capacitance betweenthe electrode 601 and the CCD substrate.

If the CCD solid-state image pickup element is driven by verticaltransfer pulses ΦV different in phase as shown in FIG. 4B, VSUBvariations responsive to the phase difference of the output voltage Voutappear, and a noise component appears in the image. FIG. 4C will bediscussed later.

The effect of the grounding resistor R61 in the vertical transferelectrode 12 is described more in detail with reference to FIGS.5A1-5B2. FIG. 5A1 illustrates an equivalent circuit to obtain a stepresponse of the output voltage Vout without the grounding resistor R61(with the resistance value of the grounding resistor R61 being zero).FIG. 5A2 illustrates a response waveform. FIG. 5B1 illustrates anequivalent circuit to obtain a step response of the output voltage Voutwith the grounding resistor R61 (with the resistance of the groundingresistor R61 being nonzero). FIG. 5B2 illustrates a response waveform.The response waveforms of FIG. 5A2 and FIG. 5B2 are obtained in asimulation test.

Referring to FIGS. 5A1 and 5B1, a resistor R44 is the sum of an outputresistor (output impedance Ro) of the vertical driver 40 and a resistorR62 as a wiring resistance of the vertical transfer electrode 12(Ro+R62). In this case, the output resistance of the vertical driver 40is mainly equivalent resistance of the switches 48 and 49 (equivalentimpedance).

In the equivalent circuit shown in FIGS. 4A and 4B and FIGS. 5A1 and5B1, the step response of the output voltage Vout (with the verticaltransfer pulse ΦV of an voltage amplitude V supplied) is represented inthe following equation (1):

Output voltage Vout(t)=V·[1−(Ro/(Ro+R61))·exp(−t/(C62(Ro+R61)))]  (1)

When time t=0, t=0 is substituted in equation (1), and the outputvoltage Vout at t=0 is obtained as represented in equation (2):

Output voltage Vout(0)=V·(R61/(R61+Ro)  (2)

FIG. 5A2 illustrates the response waveform of the output voltage Voutwith no grounding resistor, namely, with R61=0. FIG. 5B2 illustrates theresponse waveform of the output voltage Vout with a grounding resistor,namely, with R61≠0. As shown, line segment L1 represents a responsewaveform responsive to a rectangular vertical transfer pulse ΦV (=V1)supplied to the vertical transfer electrode 12, line segment L2represents a response waveform with the resistor Ro having a smallerresistance value, and line segment L3 represents a response waveformwith the resistor Ro having a larger resistance value.

As shown in FIGS. 5A2 and 5B2, the output voltage Vout sharply rises atthe rising edge at time t=0 if the equivalent resistor R61 of the CCDsubstrate is not zero (normally not zero). At a falling edge at timet=1, the output voltage Vout sharply falls.

At the moment the voltage represented by equation (1) is generated inthe electrode 601 in the CCD solid-state image pickup element 60, adriving voltage resulting in a response different from that of the abovementioned output voltage Vout is supplied to another electrode 602. Acapacitor C64 as a capacitance between the electrode 601 and theelectrode 602 and an output impedance of the driver 70 form adifferentiating circuit, thereby causing the output voltage Vout toaffect (interfere with) the electrode 602. The effect becomes pronouncedparticularly when the output voltage Vout sharply rises at time t=0.

If the equivalent resistor R61 of the CCD substrate is not zero(normally not zero), a voltage V603(t) observed at the terminal 603becomes as represented by equation (3). At time t=0, the voltage affects(interferes with) the electrode 602 via the capacitor 603.

V603(t)=V·(R61/(Ro+R61))·exp(−t/(C62(Ro+R61)))  (3)

A transient variation in the driving voltage to one electrode interfereswith a driving voltage to another electrode, thereby causing imagedegradation such as cross-talk noise. To prevent the image degradation,vertical driving (vertical transfer) is performed within the horizontalblanking period not in the effective horizontal scanning period in theknown art. This presents difficulty in increasing the transfer speed inthe CCD solid-state image pickup element.

As one solution to the noise problem, the use of the vertical transferpulse ΦV having a milder transient characteristic instead of a typicalvertical transfer pulse ΦV having a sharp transient characteristic hasbeen proposed in Japanese Unexamined Patent Application Publication No.2005-269060 (Japanese Patent Application No. 2004-076598) and JapanesePatent Application No. 2005-162034, each assigned to the same assigneeof this invention. More specifically, a mechanism of transferring signalin the vertical transfer register 13 of the image pickup section 10 awith the vertical transfer pulse ΦV having a milder transientcharacteristic (or driving method using a slow transient speed) has beenproposed. However, the driving method at the slow speed is found to beinsufficient with some noise problem remaining unresolved.

Japanese Unexamined Patent Application Publication No. 2005-028606assigned to the same assignee of this invention discloses acomplementary driving method for driving the vertical transfer registerswith the driving signals alternately inverted phase, every set ofdriving signals, namely, every two types of driving signals in additionto the slow transient speed driving.

As previously discussed, with the grounding resistor (R61≠1), theresponse waveform of the output voltage Vout sharply rises at the risingedge at time t=0 and sharply falls at the falling edge at time t=1 withthe effect of the grounding resistor R61 as shown in FIG. 5B2. This issupported by the fact that V603(0)=V(R61/(Ro+R61)) at time t=0 inequation (3) and that at time t=1, V603(1)=V(1−(R61/(Ro+R61))), althoughprocess to this conclusion is not discussed here. The sharp rising edgeand the sharp falling edge cause noise on the image.

If the complementary driving with the two driving signals inverted inphase is performed, the noise components arising from the drivingsignals also become opposed in phase, thereby canceling each other. Thecross-talk noise generated during the charge transfer in the columndirection is thus reduced.

A further mechanism for enhancing the noise control effect isincorporated as described below.

First Embodiment Noise Control Technique

FIGS. 6A and 6B and FIGS. 7A and 7B illustrate a noise control method ofa first embodiment of the present invention. FIGS. 6A and 6B are timingdiagrams illustrating driving timing for driving the CCD solid-stateimage pickup element 10 of FIG. 1 in accordance with the firstembodiment of the present invention. FIGS. 7A and 7B are timing diagramsillustrating the driving timing of a comparative example.

The control method of the first embodiment of the present invention isrelated to the four types of timing of the vertical transfer pulses ΦVsupplied to the vertical transfer electrodes 12 for vertically drivingthe vertical transfer registers 13.

In the CCD solid-state image pickup element 10, the signal charge isreceived by and photoelectrically converted by the photo sensor 11 inresponse to the amount of light and is then stored in photo sensor 11.The signal charge of the photo sensor 11 is then read into the verticaltransfer registers 13 during the vertical blanking period. The signalcharge of one horizontal line is vertically transferred toward thecharge storage section 10 b and the horizontal transfer registers 14 inthe vertical line shifting. The signal charge is thus transferred to thehorizontal transfer registers 14. The signal charge transferred to thehorizontal transfer registers 14 is transferred to the outside via theoutput amplifier 16 and the correlated double sampling circuit 17 duringthe effective horizontal transfer period.

Low-Speed Transient Driving

The vertical line shift in the driving method of the first embodimentfeatures two-phase vertical transfer. At a first phase of verticaltransfer, the vertical transfer (vertical line shift) is performed fromthe image pickup section 10 a to the charge storage section 10 b withthe vertical transfer electrodes 12_1 through 12_4 respectively suppliedwith the vertical transfer pulses ΦV_1 through ΦV_4. At a second phaseof vertical transfer, the storage gate section STG is supplied withstorage gate pulse ΦVSTG and the hold gate section HLG is supplied withthe hold gate pulse ΦVHLG.

As shown in FIG. 6A, low-speed transient driving (first-phase verticalline shift) is performed using the vertical transfer pulse ΦV with aslow transient speed during the effective horizontal scanning period Hs,while high-speed transient driving (second-phase vertical line shift) isperformed using the transfer pulses having a sharp transientcharacteristic (storage gate pulse ΦVSTG and hold gate pulse ΦVHLG)during the horizontal blanking period Hb. In this way, noise appearingduring the effective image presentation is reduced and the horizontalblanking period Hb is shortened. As a result, high speed reading isperformed.

As a two-phase mechanism to perform the charge vertical transfer, thecharge storage section 10 b including the storage gate section STG andthe hold gate section HLG is arranged between a transfer sectionincluding the vertical transfer electrode 12_4 of the vertical transferregister 13 in the image pickup section 10 a and the horizontal transferregister 14.

When the vertical line shift is performed during the effectivehorizontal scanning period Hs, the effect of cross-talk noise due to thevertical transfer pulses ΦV_1 through ΦV_4 in the CCD transfer section,namely, the effect of cross-talk noise arising from transients, or arising edge Tr and a falling edge Tf of these clock waveforms becomes aconcern. In accordance with the first embodiment of the presentinvention, the gradient ΔV/ΔT (ΔV is pulse voltage and ΔT is time) ofthe rising edge Tr and the falling edge Tf of the vertical transferpulses ΦV_1 through ΦV_4 in the vertical line shift is reduced as shownin FIG. 6A to slow the transient speed. The transient speed ΔV/ΔT isslowed to the extent that the cross-talk noise generated with thevertical transfer pulses ΦV_1 through ΦV_4 applied is removed by thecorrelated double sampling circuit 17.

Tests made with the transient speed of the vertical transfer pulses ΦV_1through ΦV_4 slowed shows that if the transient speed ΔV/ΔT is 50 mV/nsor less (not including zero), the cross-talk noise generated in thevertical line shift is removed by the correlated double sampling circuit17. Even if the vertical line shift is performed during the effectivehorizontal scanning period Hs, the effect of video noise (verticalstreaks) to the output of the CCD solid-state image pickup element isreduced. More specifically, the cross-talk noise responsive to thevertical driving pulse having the transient speed ΔV/ΔT being 50 mV/ns(not including zero) contains no high frequency components and issufficiently removed by the correlated double sampling circuit 17.

The transient speed ΔV/ΔT of the vertical transfer pulse in the knownvertical line shift is about 1 V/ns, and the cross-talk noise arisingfrom that vertical transfer pulse contains a high frequency componentthe CDS circuit cannot remove.

FIG. 6A illustrates as a ramp waveform a transient period of the clockof the vertical transfer pulses ΦV_1 through ΦV_4 in the effectivehorizontal scanning period Hs. It is sufficient if the transientcharacteristic of the riding edge Tr and the falling edge Tf, namely,the gradient of the of the riding edge Tr and the falling edge Tf of thevertical transfer pulses ΦV_1 through ΦV_4 is small. The riding edge Trand the falling edge Tf are not limited to the ramp waveform and may berising and falling at an exponential rate or a step rate. If the ridingedge Tr and the falling edge Tf are changed at a step rate, the rate ofchange at each step may be set to be as small as possible, in otherwords, a large number of steps may be incorporated.

In accordance with the first embodiment, the transient speed of thevertical driving pulse applied to the transfer electrode in the verticalline shift during the effective horizontal scanning period Hs is set tobe low. As shown in FIG. 6B, the transient speed of the verticaltransfer pulse ΦV applied to the transfer electrode during the verticalblanking period Vb is set to be high to achieve high speed transfer. Inan electronic image stabilization operation of a camcorder needing highspeed operation, or in a CCD solid-state image pickup element of frameinterline transfer (FIT) system for business use, high speed drivingneeds to be performed during the vertical blanking period Vb. The highspeed driving during the vertical blanking period is performed by thestandard CMOS driver with the vertical transfer electrodes 12_1 through12_4 supplied with the vertical transfer pulses ΦV_1 through ΦV_4 havingthe high transient speed.

A two-speed driver may be used to perform the high speed driving withinthe vertical blanking period Vb and the low speed driving within thehorizontal blanking period Hb.

The image pickup section 10 a performs the low speed transient drivingto transfer charge to the charge storage section 10 b. The vertical lineshift is performed with a small gradient of the vertical transfer pulsesΦV_1 through ΦV_4, namely, a low transient speed ΔV/ΔT. The cross-talknoise generated with the vertical transfer pulses ΦV_1 through ΦV_4applied can be removed by the correlated double sampling circuit 17. Thevideo noise (vertical streaks) is thus controlled.

The charge storage section 10 b performs the high speed transientdriving to transfer charge to the horizontal transfer register 14 withthe storage gate pulse ΦVSTG and the hold gate pulse ΦVHLD. The signalcharge can thus be transferred from the charge storage section 10 b tothe horizontal transfer register 14. The horizontal blanking period Hbis thus shortened. A high frame rate results.

Since the storage gate section STG and the hold gate section HLG can bedesigned regardless of the vertical pixel pitch, the electrode width ofthe storage gate electrode 21 and the hold gate electrode 22 can beincreased. The electrodes 21 and 22 can be reduced in resistance. Thesignal charge can be easily transferred from the storage gate sectionSTG to the horizontal transfer register 14. Lined wiring is easy todesign, and low resistant electrodes 21 and 22 are incorporated, andhigh speed transfer is achieved. The signal charge can be transferred tothe horizontal transfer registers 14 within a short horizontal blankingperiod Hb. Even higher frame rate can be achieved.

With the low transient speed driving incorporated, the vertical lineshift driving is performed at the speed switched between the high speedand the low speed. Even if the first-phase vertical line shift isperformed during the effective horizontal scanning period Hs, the videonoise (vertical streaks) does not appear because the vertical transferpulse ΦV is a low speed transient. Since the second-phase vertical lineshift is performed with the vertical transfer pulse ΦV having the highspeed transient during the horizontal blanking period Hb, the horizontalblanking period Hb can be substantially reduced in time. A high framerate results. This driving method is applicable to the high speedapplications such as the electronic image stabilization operation in thecamcorder or the business FIT application.

Complementary Driving

In the driving method of the first embodiment, every plural number ofvertical transfer electrodes 12 are grouped into sets, which aresupplied with alternately reversed vertical transfer pulses ΦV. In otherwords, the vertical transfer pulses ΦV are used in a complementarymethod. The driving method of the first embodiment is substantiallydifferent from the driving method of FIGS. 7A and 7B in which the fourtypes of driving pulses different in phase are supplied.

For example, the vertical transfer electrodes 12 in the image pickupsection 10 a of the CCD solid-state image pickup element 10 has atwo-layer structure. If the vertical transfer electrodes 12 identical instructure are driven with the driving pulses in the complementaryfashion, voltage fluctuations caused by the coupling capacitance betweenthe vertical transfer electrode 12 and each of the PWELL-#2 b and thesemiconductor substrate SUB can cancel each other.

The complementary driving (reverse phase driving) allows the period ofthe vertical transfer pulse ΦV to be halved, and as a result, thetransient period can be doubled. The transient speed can thus lowered,allowing the cross-talk noise to be reduced.

With the cross-talk noise reduced, the output amplifier 16 is free fromnoise problem even if the output amplifier 16 is designed to have highgain. High speed and high gain performance is thus provided.

Major Advantages of Complementary Driving

FIGS. 8A-8C and FIGS. 9A and 9B illustrates major advantages of thecomplementary driving. FIGS. 8A-8C illustrate the relationship betweenthe equivalent circuit of the vertical driver and the CCD solid-stateimage pickup element 30. FIGS. 9A and 9B illustrate the principle of avertical driver 50 that reduces the transient speed.

As shown in FIG. 8A, the CCD solid-state image pickup element 10 isreferred to as the CCD solid-state image pickup element 60 in theequivalent circuit as in FIG. 4A. The CCD solid-state image pickupelement 60 is driven by the driving circuit 5. The driving circuit 5includes the vertical driver 50 unique to this embodiment that suppliesto the vertical transfer electrode 12 the vertical transfer pulse ΦV,the storage gate pulse ΦVSTG, and the hold gate pulse ΦVHLG.

The vertical driver 50 generates the vertical transfer pulses ΦV_1through ΦV_4, and the CCD solid-state image pickup element 60 includesthe vertical transfer electrodes 12_1 through 12_4 respectively suppliedwith the vertical transfer pulses ΦV_1 through ΦV_4. As shown in FIGS.8A and 8B, the vertical driver 50 generates a single vertical transferpulse ΦV (output voltage Vout) for simplicity of explanation, but theCCD solid-state image pickup element 60 is driven by a plurality ofdrivers (for example, another vertical driver and another horizontaldriver 70).

When an electrode 68 is supplied with a vertical transfer pulse ΦV_1 inthe complementary driving of FIGS. 8A and 8B, an electrode 69 issupplied with the vertical transfer pulse ΦV_3 reverse in phase to thevertical transfer pulse ΦV_1. When the electrode 68 is supplied with thevertical transfer pulse ΦV_2, the electrode 69 is supplied with thevertical transfer pulse ΦV_4 reverse in phase to the vertical transferpulse ΦV_2.

The vertical driver 50 includes an inverter 51 for logically inverting acontrol signal Din input via a terminal 503, a level shift (L/S) circuit52 for outputting a control signal Vg1 responsive to the level of thecontrol signal Din input via the terminal 503, and a level shift circuit53 for outputting a control signal Vg2 responsive to the level of acontrol signal NDin that is logically inverted by the inverter 51 fromthe control signal Din input via the terminal 503.

The vertical driver 50 includes a voltage output section 54 and animpedance controller 55 as stages subsequent to the level shift circuits52 and 53. The voltage output section 54 receives constant voltages V1and V2 (voltage value V) via terminals 501 and 502, and outputs one ofthe input voltages as a output voltage Vout via an output terminal 504to the CCD solid-state image pickup element 60. For example, the voltageV1 is at a high level, and the voltage V2 is at a low level.

The impedance controller 55 controls the output impedance viewed fromthe output terminal 504 in accordance with transfer characteristic ofthe CCD solid-state image pickup element 60 serving as a capacitiveload. As shown in FIGS. 8A and 8B, the impedance controller 55 includesa plurality of cascaded delay lines (delay elements) 56 (individuallyidentified by suffixes _1, _2, . . . , _m), a plurality of cascadeddelay lines (delay elements) 57 (individually identified by suffixes _1,_2, . . . , _m), and switches 58 and 59 (individually identified bysuffixes _1, _2, . . . , _m) respectively arranged for the delay lines56 and 57. As will be described later, the switches 58 and 59 are set tobe turned on and off in accordance with the transfer characteristics ofthe CCD solid-state image pickup element 60.

The vertical driver 50 drives the electrode 601 as one electrode of theCCD solid-state image pickup element 60 with the output voltage Voutwhile the driver 70 as the other vertical driver and the horizontaldriver drives the electrode 602 as the other electrode of the CCDsolid-state image pickup element 60.

The delay line 56 and the switch 58 control the output impedance atwhich the voltage V1 is output as the output voltage Vout from theterminal 501 and the delay line 57 and the switch 59 control the outputimpedance at which the voltage V2 is output as the output voltage Voutfrom the terminal 502.

The delay line 56 and the switch 58 are constructed as described below.One end of each of the switches 58 is commonly connected to the terminal501 (voltage V1) while the other end of each of the switches 58 iscommonly connected to the output terminal 504. The switches 58 arearranged at the front and back of each delay line 56. As the controlsignal Vg1 from the level shift circuit 52 travels along the delay lines56, the switch 58_1 through the switch 58 _(—) m are successively turnedon with a delay introduced.

Each switch 58 contains an impedance component. As the switches 58 areturned on with the control signal Vg1 traveling along the delay lines56, the value of the parallel impedance created by the switches 58becomes smaller. More specifically, the output impedance of the verticaldriver 50 viewed from the output terminal 504 is successively reduced.

Similarly, one end of each of the switches 59 is commonly connected tothe terminal 502 (voltage V2) while the other end of each of theswitches 59 is commonly connected to the output terminal 504. Theswitches 59 are arranged at the front and back of each delay line 57. Asthe control signal Vg2 from the level shift circuit 53 travels along thedelay lines 57, the switch 59_1 through the switch 59 _(—) m aresuccessively turned on with a delay introduced.

Each switch 59 contains an impedance component. As the switches 59 areturned on with the control signal Vg2 traveling along the delay lines57, the value of the parallel impedance created by the switches 59becomes smaller. More specifically, the output impedance of the verticaldriver 50 viewed from the output terminal 504 is successively reduced.

In the vertical driver 50, the control signal Din is input via theterminal 503, the level shift circuits 52 and 53 supply the controlsignals Vg1 and Vg2 for turning on the switches 58 and 59 to the delaylines 56 and 57, respectively. More specifically, the inverter 51transitions the input signal to one of the level shift circuits 52 and53 to a high level, thereby causing the output signal from the one ofthe level shift circuits 52 and 53 to travel along the delay lines, andthe corresponding switches to be successively turned on.

With the impedance controller 55 controlling the output impedance of thevertical driver 50, the transient speed ΔV/ΔT of the output voltage Voutis reduced.

FIG. 8A, corresponding to FIGS. 5A1 and 5B1, shows an equivalent circuitfor determining a step response of the output voltage Vout. FIG. 8B,corresponding to FIGS. 5A2 and 5B2, shows response waveforms. Theresponse waveform of FIG. 8B is obtained in the equivalent circuitwithout the capacitor 62.

As shown in FIG. 8A, an impedance Z58 is the sum of an output impedanceZo viewed from the output terminal of the vertical driver 50 and aresistor R62 as a wiring resistance of the vertical transfer electrode12 (Zo+R62). The Zo of the vertical driver 50 is mainly an equivalentimpedance of each of the switches 58 and 59. The output impedance Zo ofthe vertical driver 50 changes with time in accordance with equationZo(t)=rs0 exp(−αt) (rs0: initial value=Zo(0), and α: constant).

The step response of the output voltage Vout (with the vertical transferpulse ΦV having an voltage amplitude V supplied) in the equivalentcircuit of FIG. 9A is determined as described in equation (4-1). If theresistor R62 as the wiring resistance of the vertical transfer electrode12 is neglected, equation (4-2) results. If the capacitor C62 is notcontained, equation (4-3) results:

Output voltageVout(t)=V·[1−(Z58(t)/(Z58(t)+R61))·exp(−t/(C62(Z58(t)+R61)))]  (4-1)

Output voltageVout(t)=V·[1−(Zo(t)/(Zo(t)+R61))·exp(−t/(C62(Zo(t)+R61)))]  (4-2)

Output voltage Vout(t)=V·R61/(R61+Zo(t))=R61/(R61+rs0·exp(−αt))  (4-3)

Particularly, when time t=0, t=0 is substituted in equations (4-2) and(4-3), the output voltage Vout at time t=0 is obtained as expressed byequation (5):

$\begin{matrix}\left. \begin{matrix}{{{Output}\mspace{14mu} {voltage}\mspace{14mu} {{Vout}(0)}} = {V \cdot \left( {R\; {61/\left( {{R\; 61} + {{Zo}(0)}} \right)}} \right.}} \\{= {V \cdot \left( {R\; {61/\left( {{R\; 61} + {{rs}\; 0}} \right)}} \right.}}\end{matrix} \right\} & (5)\end{matrix}$

In comparison of equation (5) with the conventional output voltageVout(0)=V R61/(R61+Ro) (see equation (2)), the value of the outputvoltage Vout at t=0 is reduced more than in the known art by adjustingthe initial value rs0 of the output impedance Zo of the vertical driver50. For example, if rs0=8Ro, the value of the output voltage Vout at t=0becomes one-eighth the value of the known art. Since the value of theimpedance Z58 is large, the transient characteristic of the outputvoltage Vout is made smooth, namely, the transient speed of the outputvoltage Vout is lowered.

There is a possibility that the transient speed is excessively loweredwith the output voltage Vout failing to reach the standard level (=V)within the active period of the vertical transfer pulse ΦV, and that thevertical transfer electrode 12 is not sufficiently driven.

To overcome this drawback, the output impedance Zo of the verticaldriver 50 is lowered with time. If the output impedance Zo of thevertical driver 50 is exponentially lowered, the transient responsecharacteristic of the output voltage Vout (with the capacitor C62 notincluded) is set to be milder as shown in FIG. 9B, more specifically,the transient speed of the output voltage Vout is lowered.

In the equivalent circuit of FIG. 9A, the output impedance Zo of thevertical driver 50 is expressed by an exponential function. At time t=0,the initial value rs0 plays an important factor in lowering thetransient speed of the output voltage Vout, and expressing the outputimpedance Zo of the vertical driver 50 with the exponential function isnot necessary. However, the transfer characteristic of the CCDsolid-state image pickup element 60 as the capacitive load expressed intime axis typically has an exponential factor. If the output impedanceof the vertical driver 50 also has an exponential factor in time axis,the transient characteristic of the output voltage Vout becomespreferably milder.

In accordance with the exponential factor of the transfer characteristicof the CCD solid-state image pickup element 60 expressed in time axis,the impedance of the switches 58 and 59 is ideally exponentially reducedwith the switches 58_1, 58_2, . . . , 58 _(—) m.

The equivalent capacitance of the electrodes of the CCD solid-stateimage pickup element is largely dependent on the number of pixels, usedprocess, and the layout configuration (collectively referred to asdevice characteristic). The transient characteristic of the drivingvoltage of the known vertical driver optimized for a particular CCDsolid-state image pickup element is not necessarily optimum for anotherCCD solid-state image pickup element. A method of controlling thetransient characteristic of the driving voltage response to the CCDsolid-state image pickup element is desired.

The impedance value of the switches 58 and 59 is preferably set inaccordance with the transfer characteristic of the CCD solid-state imagepickup element 60 as a capacitive load. In particular, the lower theoutput voltage Vout, namely, the higher the initial value rs0 of theimpedance as shown in FIG. 9B, the better to achieve a low transientspeed. In the vertical driver 50, the impedance of the switches 58_1 and59_1 that become the output impedance at t=0 is set to be the highest.With the impedance of the switches 58_1 and 59_9 set to be appropriate,the value of the output voltage Vout at t=0 becomes sufficiently small,and provides advantages over the known art.

The output impedance Zo of the vertical driver 50 at the rising edge(t=0) and the falling edge (t=1) is set to be large. As time elapses,the output impedance Zo is reduced. Even if the vertical transferelectrodes 12 are driven by the driving pulse having a low transientspeed, the output voltage Vout(0)=V(R61/(R61+rs0)) or output voltageVout(1)=V(1−(R61/(R61+rs0))) still remains. In response to a voltagechange, vertical streaks as the cross-talk noise appears on a screen anda voltage change during a transient period still appears on the screen.

As previously discussed with reference to FIGS. 8A-8C, the electrode 601as one electrode of the CCD solid-state image pickup element 60 in theequivalent circuit is driven by the vertical driver 50 while theelectrode 602 as the other electrode is driven by the other driver 70. Atransient change in the driving voltage to the other electrode 602interferes with the driving voltage to the electrode 601.

In accordance with the driving method using the low transient speedproposed in Japanese Patent Applications Nos. 2004-076598 and2005-162034, the CCD solid-state image pickup element is driven by thefour types of vertical transfer pulses ΦV different in phase as shown inFIGS. 7A and 8B. Even if the vertical transfer pulse ΦV having the lowtransient speed is used, a noise component responsive to phase differentappears, and cross-talk noise still remains.

In contrast, if every two vertical transfer electrodes 12 are grouped insets, which are driven by the vertical transfer pulse ΦV in acomplementary driving, namely, driven by alternately reversed phased,vertical transfer pulses ΦVa and ΦVb, voltage variations with theelectrode 601 driven by the vertical transfer pulse ΦVa and voltagevariations with the electrode 602 driven by the vertical transfer pulseΦVb cancel each other. As a result, voltage fluctuations caused by thecoupling capacitor between the vertical transfer electrode 12 and eachof the PWELL-#2 b and the semiconductor substrate SUB becomeapproximately zero.

To cancel voltage variations with alternately reversed phase voltages,symmetry of electrodes becomes a concern. In the two-layer electrode andfour-phase driving shown in FIG. 2, the vertical transfer electrodes 12to be driven by the alternately reversed phase voltages include thesecond layer vertical transfer electrodes 12_1 and 12_3 and the firstlayer vertical transfer electrodes 12_2 and 12_4. Since the first layerelectrodes are identical to each other in pattern shape and the secondlayer electrodes are identical to each other in pattern shape, thecapacitances are balanced and the noise canceling effect of thecomplementary driving is large.

Even if the electrode structure is not well balanced, the cross-talknoise may still be minimized by adjusting the driving capability of thevertical driver 50, more specifically, by adjusting the voltageamplitude of the driving pulse.

Additional Advantages of the Complementary Driving

FIG. 10 illustrates additional advantages of the complementary driving.In the complementary driving of the first embodiment of the presentinvention, the first-phase vertical line shift is performed with thevertical transfer pulses ΦV_1 through ΦV_4 having the low transientspeed more slowly than the transient driving method with the lowtransient disclosed in Japanese Patent Application Nos. 2004-076598 and2005-162034. Thinner design can thus be incorporated in the verticaltransfer electrodes 12_1 through 12_4.

As shown in FIG. 10, the CCD solid-state image pickup element 10includes the vertical transfer register 13 including the photo sensor11, the readout gate section ROG, the embedded channel region 24, andthe vertical transfer electrode 12 on the gate dielectric layer 25. Athickness d0 of the vertical transfer electrode 12 is made thinner thana thickness d2 in the known art or a thickness d1 described JapanesePatent Application Nos. 2004-076598 and 2005-162034. The height of thestep defining the sensor aperture 118 is substantially reduced so thatthe blocking effect to an obliquely entering light ray (solid line) L0is minimized.

This arrangement increases the size of the sensor aperture 118, improvesthe light collection efficiency to the obliquely entering light ray, andleads to high sensitivity. Since the blocking of the obliquely enteringlight ray is controlled, the generation of shading is also reduced. Anobliquely entering light ray L1 (represented by dot-and-dash chain line)shows the light blocked state with the thickness d1 described inJapanese Patent Application Nos. 2004-076598 and 2005-162034, and anobliquely entering light ray L2 (represented two-dot-and-dash line)shows the light blocked state of the known obliquely entering light ray.

Example of Driving Timing

FIGS. 11 through 18 illustrate examples of other driving timings. In theabove discussion, the four types of the vertical transfer pulses ΦV areused. The vertical transfer pulses ΦV are not limited to the four types.For example, FIG. 11 illustrates a conventional eight-phase drivingmethod that uses successively eight types of vertical transfer pulsesΦV. In contrast, FIG. 12 illustrates that two types of vertical transferpulses ΦV of the eight types are reversed phased. More specifically, thevertical transfer pulses ΦV_1 and ΦV_3 are reverse to each other inphase, the vertical transfer pulses ΦV_2 and ΦV_4 are reverse to eachother in phase, the vertical transfer pulses ΦV_3 and ΦV_5 are reverseto each other in phase, the vertical transfer pulses ΦV_4 and ΦV_6 arereverse to each other in phase, the vertical transfer pulses ΦV_5 andΦV_7 are reverse to each other in phase, the vertical transfer pulsesΦV_6 and ΦV_8 are reverse to each other in phase, the vertical transferpulses ΦV_7 and ΦV_1 are reverse to each other in phase, and thevertical transfer pulses ΦV_8 and ΦV_2 are reverse to each other inphase.

Even when the a moving picture pickup and driving on a VGA mode usingthe conventional eight-phase driving method, two of the eight phasevoltages may be reversed as shown in FIG. 13. More specifically, thevertical transfer pulses ΦV_1 and ΦV_4 are reverse to each other inphase, the vertical transfer pulses ΦV_2 and ΦV_5 are reverse to eachother in phase, the vertical transfer pulses ΦV_3 and ΦV_6 are reverseto each other in phase, the vertical transfer pulses ΦV_4 and ΦV_7 arereverse to each other in phase, the vertical transfer pulses ΦV_5 andΦV_8 are reverse to each other in phase, the vertical transfer pulsesΦV_6 and ΦV_1 are reverse to each other in phase, the vertical transferpulses ΦV_7 and ΦV_2 are reverse to each other in phase, and thevertical transfer pulses ΦV_8 and ΦV_3 are reverse to each other inphase.

Pseudo-Complementary Driving

In the above example, two types are reversed to each other in driving.As shown in FIGS. 14 and 15, one type of driving signal is combined witha plurality of other types of driving signal so that the driving signalsare reverse to each other as a whole. More specifically, at least everythree types of driving signals are grouped in a set so that the threetypes of driving signals achieve the reverse driving effect. Preferably,the low transient speed may be combined with the complementary drivingmethod. As shown in FIG. 14, the transient speed is set to be evenslower.

As shown in FIGS. 14 and 15, one driving signal is grouped with aplurality of other driving signals to achieve the reverse driving state.As shown in FIG. 16, it is acceptable if the driving signals arepartially discontinued. FIG. 16 illustrates four-phase pseudo-reverse(complementary) driving, which is appropriate for use in driving amoving picture on a mega pixel CCD solid-state image pickup element.

FIG. 17 illustrates a conventional five-field, ten-phase successivedriving method using ten types of vertical transfer pulses ΦV. As shownin FIG. 18, predetermined two types of the ten types are set to bereverse to each other in phase.

When the vertical transfer electrodes 12 are supplied with thesubstantially rectangular driving signals in the known art as shown inFIG. 4C, the use of the reverse driving method of the first embodimentcontrols VSUB variations, thereby controlling the video noise component.However, there is a possibility that a slight phase shift leads to aspike voltage fluctuation as video noise.

Second Embodiment Noise Control Technique

FIG. 19 illustrates a noise control method in accordance with a secondembodiment of the present invention. The noise control method of thesecond embodiment relates to an active control method that activelycontrols noise arising from cross-talk noise (coupling noise) induced onPWELL-#2 b and the semiconductor substrate SUB in the CCD solid-stateimage pickup element.

The conventional vertical driver 40 is used as a vertical driver, andvertical transfer pulses ΦV different in phase having a sharp transientcharacteristic as in the known art are used.

As shown in the sectional view of FIG. 3C, the VSUB terminal 130 on thesemiconductor substrate NSUB is supplied with the DC bias Vbias, and thePWELL ground terminal 132 of the PWELL-#2 a on the side of the outputamplifier 16 is connected to the ground GND. Using these terminals, anoise correction signal is supplied from the outside to cancel thecoupling noise.

As shown in FIG. 19, a image pickup device 1 of the second embodimentincludes the CCD solid-state image pickup element 30 and the verticaldriver 40, each identical to those of the known art. In addition, theimage pickup device 1 includes a noise correction signal supply circuit200 as a feature of the second embodiment of the present invention.

The noise correction signal supply circuit 200 includes a phaseinverting circuit (inverting amplifier) 210 for inverting the verticaltransfer pulse ΦV supplied from the vertical driver 40 to supply thephase inverted pulse to each of the VSUB terminal 130 and the PWELLground terminal 132. The noise correction signal supply circuit 200further includes a waveform shaping circuit 220. The noise correctionsignal supply circuit 200 thus provides the VSUB terminal 130 and thePWELL ground terminal 132 with a waveform reverse in phase to noisetransferred from the output terminal of the vertical driver 40 to thePWELL-#2 b and the semiconductor substrate SUB.

The waveform shaping circuit 220 uses the output signal from the phaseinverting circuit 210 to generate noise correction signals CompN1 andCompN2 that are reverse in phase from noise Noise1 and Noise2 caused onthe PWELL-#2 b and the semiconductor substrate SUB. In view of thecoupling noise that has differentiated characteristic, a serial circuitof a capacitor 222 and a resistor 224 is arranged to form a CRdifferentiating circuit in a manner such that the capacitor 222 isarranged on the output side of the phase inverting circuit 210 and thatthe resistor 224 is arranged the ground GND side of the phase invertingcircuit 210. The junction of the capacitor 222 and the resistor 224 isconnected to each of the VSUB terminal 130 and the PWELL ground terminal132. The VSUB terminal 130 is supplied with the DC bias Vbias, and theresistor 224 is connected to the ground GND via the DC bias Vbias.

In accordance with the second embodiment, the vertical transfer pulse ΦVsupplied from the output terminal of the vertical driver 40 is invertedin phase by the phase inverting circuit 210. The waveform shapingcircuit 220 thus shapes the output signal from the phase invertingcircuit 210 into the noise correction signals CompN1 and CompN2 that arereverse in phase from noise Noise1 and Noise2 caused on the PWELL-#2 band the semiconductor substrate SUB, and then supplies the noisecorrection signals CompN1 and CompN2 to the VSUB terminal 130 and thePWELL ground terminal 132. In this way, the coupling noise Noise1 andNoise2 arising from the cross-talk on the PWELL-#2 b and thesemiconductor substrate SUB in the CCD solid-state image pickup elementis thus cancelled by the noise correction signals CompN1 and CompN2reverse in phase, and the vertical streak noise is controlled.

Since the coupling noise Noise1 and Noise2 caused on the PWELL-#2 b andthe semiconductor substrate SUB in the CCD solid-state image pickupelement depends on the device characteristic and the transientcharacteristic of the vertical transfer pulse ΦV, amplifier gain of thephase inverting circuit 210 and the CR time constant of the waveformshaping circuit 220, optimized for a given CCD solid-state image pickupelement, are not necessarily optimum for another CCD solid-state imagepickup element. The actually optimized noise correction signals CompN1and CompN2 can be generated by adjusting the amplifier gain and the CRtime constant in accordance with the transient characteristics of theCCD solid-state image pickup element and the vertical transfer pulse ΦV.

The noise correction signals CompN1 and CompN2 are generated using acombination of the inverting amplifier and the CR differentiatingcircuit. This arrangement is quoted for exemplary purposes only. Anothercircuit arrangement may be employed. It is important that a reversephase signal be generated in a waveform matching the characteristic ofthe actual coupling noise Noise1 and Noise2.

The known vertical driver 40 is herein used as a vertical driver, andvertical transfer pulses ΦV different in phase having a sharp transientcharacteristic as in the known art are used. The vertical transferpulses ΦV different in phase and having low transient speed disclosed inJapanese Patent-Applications Nos. 2004-076598 and 2005-162034 and thenoise control method of the first embodiment of reverse phase driving atlow transient may be combined.

Third Embodiment Noise Control Technique

FIGS. 20A-20E illustrate a noise control method of a third embodiment ofthe present invention. The noise control method of the third embodimentrelates to a noise control circuit such as a low-pass filter arrangedbetween a vertical driver and a CCD solid-state image pickup element.The third embodiment is largely different from the known art because itis considered important in the known art that the driving signal fromthe vertical driver should be transferred to a vertical transferelectrode in a form as close as possible to the original shape thereof.

If the vertical transfer pulse ΦV supplied from the vertical driver 40is supplied to the vertical transfer electrode via the noise controlcircuit, the cross-talk noise due to spike noise can be reduced even ifunpredicted spike noise is generated in the output of the verticaldriver.

The known vertical driver 40 is herein used as a vertical driver, andvertical transfer pulses ΦV different in phase having a sharp transientcharacteristic as in the known art are used. The third embodiment may becombined with the use of the vertical transfer pulses ΦV different inphase and having low transient speed disclosed in Japanese PatentApplications Nos. 2004-076598 and 2005-162034, the noise control methodof the first embodiment of reverse phase driving at low transient, andthe noise control method of the second embodiment of supplying the noisecontrol signal in phase reverse to the noise generated in the CCDsolid-state image pickup element.

The noise control circuit may provide a noise control effect on its own,or may provide a noise control effect in combination with the elementfunction of the vertical driver 40 and a CCD solid-state image pickupelement 80.

FIG. 20A illustrates an equivalent circuit of a connection between theknown vertical driver and the CCD solid-state image pickup element. Asshown in FIG. 20A, the CCD solid-state image pickup element 30 isillustrated as the CCD solid-state image pickup element 80 in theequivalent circuit. The CCD solid-state image pickup element 80illustrated in the equivalent circuit is identical to the one of FIGS.4A and 8A only in view of the electrode 601. A capacitor C82 has acapacitance within a range of 100 to 1000 pF, a resistor R1 is on theorder of several tens of Ω, and a wiring resistor R82 of the verticaltransfer electrode 12 has a resistance within a range from several tensof Ω to several hundreds of Ω.

In contrast, a noise control circuit 310 of FIG. 20B includes acapacitor 316 between a signal line connecting the vertical driver 40 tothe vertical transfer electrode 12 and the ground GND. The capacitor 316forms an RC low-pass filter together with an output resistor Ro of thevertical driver 40 (or output impedance Zo). Even if unpredictable spikenoise takes place in the output of the vertical driver 40, thecross-talk noise responsive to the spike noise is thus reduced.

In a first example of FIG. 20B, the output register Ro of the verticaldriver 40 and the capacitor 316 form the low-pass filter. The outputresistor Ro has typically a small resistance, and to provide sufficientfiltering effect, the capacitance of the capacitor 316 is set to belarger than the counterpart in a second example and a third example.

A noise control circuit 320 as the second example shown in FIG. 20Cincludes a resistor 322 having a resistance larger than the outputresistor Ro (or output impedance Zo) in the signal line connecting thevertical driver 40 and the vertical transfer electrode 12, and acapacitor 326 arranged between a signal line extending connecting theresistor 322 to the vertical transfer electrode 12 and the ground GND.The resistor 322 and the capacitor 326 form an RC filter.

The capacitor 326 forms the RC low-pass filter in combination with aserial resistor of the output resistor Ro of the vertical driver 40 (oroutput impedance Zo) and the resistor 322. Since the resistor 322 has aresistance larger than the output resistor Ro (output impedance Zo), theresistor 322 and the capacitor 326 in practice form the RC low-passfilter. Even if unpredictable spike noise takes place in the output ofthe vertical driver 40, the cross-talk noise due to the spike noise isreduced.

Since the resistor 322 having a resistance larger than the outputresistor Ro (output impedance Zo) and the capacitor 326 form the RClow-pass filter circuit in the second example, a sufficient filter isformed even if the capacitance of the capacitor 326 is set to be smallerthan that of the counterpart 316 in the first example. With the resistor322 inserted, a voltage drop occurs between a grounding resistor R1 anda wiring resistor R82, and there is a possibility that the voltageamplitude of the vertical transfer pulse ΦV supplied to a terminal 801is reduced leading to a drop in the driving capability.

A noise control circuit 330 as a third example shown in FIG. 20Dincludes an inductor (coil) 334 in the signal line connecting thevertical driver 40 to the vertical transfer electrode 12. The inductor334 forming an L type structure has a sufficiently small equivalentresistance. The vertical transfer pulse ΦV is supplied from the verticaldriver 40 to the vertical transfer electrode 12 via the inductor 334.

The inductor 334 forms an LC low-pass filter together with the capacitorC82 in the CCD solid-state image pickup element 80. More in detail,since the grounding resistor R1 and the wiring resistor R82 are presentin the CCD solid-state image pickup element 80, an RLC low-pass filteris formed.

Even if unpredictable spike noise is created in the output of thevertical driver 40, the cross-talk noise due to the spike noise isreduced. Since the equivalent resistance of the inserted inductor 334 issmall, no drop in the driving capability occurs unlike in the secondexample using the resistor 322.

In a noise control circuit 340 as a fourth example shown in FIG. 20E, aninductor 344 having a small equivalent resistance is arranged in thesignal line connecting the vertical driver 40 to the vertical transferelectrode 12. The vertical transfer pulse ΦV is supplied from thevertical driver 40 to the vertical transfer electrode 12 via theinductor 344. Furthermore, a capacitor 346 is arranged between thesignal line connecting the inductor 344 to the vertical transferelectrode 12 and the ground GND. An LC structure is thus provided.

The inductor 344 in combination with the capacitor 346 forms an LClow-pass filter. Even if unpredictable spike noise is created in theoutput of the vertical driver 40, the cross-talk noise due to the spikenoise is reduced. Since the equivalent resistance of the insertedinductor 344 is small enough, no drop in the driving capability occursunlike in the second example using the resistor 322.

The fourth example includes the capacitor 346 in addition to thestructure of the third example. The low-pass filter circuit is formed ofthe capacitor C82 in the CCD solid-state image pickup element 80 (moreexactly, in combination with the grounding resistor R1 and the wiringresistor R82). In addition the filter effect of the third example,further filter effect is additionally provided by the capacitor 346.

The capacitor 346 directly works with the inductor 344 while thecapacitor C82 in the CCD solid-state image pickup element 80 works withthe inductor 344 via the grounding resistor R1 and the wiring resistorR82. Damping effect thus results. If the capacitances of both capacitorsare approximately the same, the capacitor 346 offers more filteringeffect.

From among the noise control circuits 310-340 of the first throughfourth examples, the fourth example provides the least drop in thedriving capability and the highest filtering effect. The fourth exampleoffers the best arrangement as an actual application followed by thethird example that offers the next least drop in the driving capability.

Fourth Embodiment Noise Control Technique

FIGS. 21A and 21B illustrate a noise control method of a fourthembodiment of the present invention. The noise control method of thefourth embodiment improves a sharp change in the output voltage Vout atthe rising edge and the falling edge of the vertical transfer pulse ΦVdue to the effect of the grounding resistor of the substrate (SUB) bychanging the substrate grounding resistor from resistive to capacitivein equivalent circuit.

The known vertical driver 40 is herein used as a vertical driver, andvertical transfer pulses ΦV different in phase having a sharp transientcharacteristic as in the known art are used. The mechanism of the fourthembodiment may be combined with each of the vertical transfer pulses ΦVdifferent in phase and having low transient speed disclosed in JapanesePatent Application Nos. 2004-076598 and 2005-162034 and the noisecontrol method of each of the first through third embodiments of reversephase driving at low transient.

As previously discussed with reference to FIGS. 3A-3C and FIGS. 5A1-5B2,the light shielding layer resistor R1 created between the lightshielding layer 119 and the ground GND and the substrate resistor R2 ofthe semiconductor substrate NSUB are present as the grounding resistor.The total grounding resistor R of these resistors is equivalent to theparallel component of the light shielding layer resistor R1 and thesubstrate resistor R2.

To make the grounding resistance from resistive to capacitive inequivalent circuit, three methods are contemplated. In a first method,the light shielding layer resistor R1 is made capacitive, in a secondmethod the substrate resistor R2 is made capacitive, and in a thirdmethod, the first method and the second method are combined. FIGS. 21Aand 21B illustrate the first method for changing the light shieldinglayer resistor R1 from resistive to capacitive.

In the first method, the noise Noise2 arising from the vertical transferpulse ΦV supplied to the vertical transfer electrode 12 fluctuates thePWELL-#2 b of the output amplifier 16 via the coupling capacitor C1, thelight shielding layer 119, the light shielding layer resistor R1 and theground GND. Because of the back gate effect of the transistor 120forming the output amplifier 16, the noise Noise2 affects the transistor120. As a result, the first method prevents noise from beingsuperimposed on the output signal, reducing vertical streak noise.

In the second method, the noise Noise1 is induced on the semiconductorsubstrate NSUB, and because of the back gate effect of the transistor120 forming the output amplifier 16, the noise Noise1 affects thetransistor 120 via the coupling capacitor C3. As a result, the secondmethod prevents noise from being superimposed on the output signal,reducing vertical streak noise.

To change the substrate grounding resistor from resistive to capacitive,a capacitor is connected in parallel with the substrate groundingresistor to form a grounding capacitive type filter. For example, thelight shielding layer resistor R1 is basically considered to be anequivalent resistor R10 of the light shielding layer 119. Connecting acapacitor to the equivalent resistor R10 via a terminal 133 is difficultin practice. On the other hand, as previously discussed with referenceto FIG. 3C, the protective resistor R12 having a resistance fallingwithin a range from several hundreds of Ω to several tens of kΩ isinserted between the light shielding layer 119 and the ground GND usingthe terminal 133 to prevent electrostatic breakdown. As shown in FIG.21A, if a capacitor 412 is connected in parallel to the protectiveresistor 12 using the terminal 133, the protective resistor R12 as aportion of the light shielding layer resistor R1 is changed fromresistive to capacitive in equivalent circuit.

A sharp change occurs in the output voltage. Vout (see FIG. 5B2) at therising edge and the falling edge of the vertical transfer pulse ΦV dueto the wiring resistor (the protective resistor R12 as a portion of thelight shielding layer resistor R1). By connecting the capacitor 412 inparallel to the protective resistor R12, a signal current flowing at therising edge and the falling edge of the vertical transfer pulse ΦV isintentionally drained along the capacitor 412. As a result, the sharpvoltage change is controlled.

Terminals other than the terminal 133 may be used for connection. Thelight shielding layer 119 generally covers the CCD solid-state imagepickup element 10. If a large number of capacitors 412 are connected atmany points to the ground GND, the resulting equivalent circuit of FIG.21A includes the capacitor 412 connected between the coupling capacitorC1 of the light shielding layer 119 and ground. In this way, the entirelight shielding layer resistor R1 becomes capacitive in equivalentcircuit.

Although the sharp change occurs in the output voltage Vout (see FIG.5B2) at the rising edge and the falling edge of the vertical transferpulse ΦV due to the wiring resistor (the protective resistor R12 as aportion of the light shielding layer resistor R1), the signal currentflowing at the rising edge and the falling edge of the vertical transferpulse ΦV is drained along the capacitor 412 by connecting the capacitor412 in parallel to the protective resistor R12. As a result, the sharpvoltage change is controlled.

FIGS. 21A and 21B illustrate the first method of changing the lightshielding layer resistor R1 from resistive to capacitive. If a number ofcapacitors are arranged in parallel between the semiconductor substrateNSUB and the ground GND, the substrate resistor R2 may be changed fromresistive to capacitive in equivalent circuit.

Effect of Variations and Environmental Changes

When the transfer electrodes of the CCD solid-state image pickup element10 are driven by the driving pulses, the transient speed of the drivingpulses may be lowered, or the complementary driving may be employed. Inthis way, both the high speed driving and the noise control areaccomplished at the same time.

The low speed driving pulse signals with a low transient speed aregenerated by the driver circuit arrangement with the output stage splitas shown in FIGS. 7A and 7B and FIGS. 8A and 8B. In this case, thedriving pulse is generated based on a time constant unique tocharacteristic such as a through rate of the output waveform, a minimumoutput gradient cannot be obtained to assure design margin. Although theoutput driving capability is varied in response to the load capacitance,the driving capability at the start of transition remains constant.These can be problematic.

When a load as a capacitive reactance is driven by a smooth and mildlyinclined gradient, low speed pulse signal, the driving of the loadcapacitance merely with a constant current is contemplated to maintainthe gradient of the driving pulse as disclosed in Japanese UnexaminedPatent Application Publication No. 2005-269060. The mere constantcurrent driving is not practical in the image pickup system.

The gradient of the driving pulse also changes in response to variationsin the manufacture of load capacitance and variations in the manufactureof driving elements. If there are variations in the load capacitancefrom channel to channel with respect to the driving characteristic whena plurality of channels are driven, the gradient of the pulse changesfrom channel to channel.

To reduce the noise component such as spike likely to occur during thetransition, the waveform of the pulse input to the prior stage of thedriving circuit needs to be smooth. This leads to an initial delay timebefore the start of the transition of the final pulse output. The delaytime depends on variations in the load capacitance and variations in thedriving elements.

If the gradient of the output becomes large, noise is likely to remainon images because of CCD noise resistance characteristics. If thegradient of the output becomes small, transition of the current outputcan overlap the transition of the next output, possibly leading toerratic transfer.

To reduce variations in the manufacture of the load capacitance andvariations in the manufacture of the driving elements, feedback controlis considered to be effective. In the feedback control, an active pulsesignal is measured, and active transient characteristics such as thedelay time of the output pulse waveform responsive to the input pulseand the through rate during the transition are converged to desiredtransient characteristics based on the measurement results. Waveformshaping function with the feedback control applied to the pulse drivingwaveform is considered to be effective. The circuit arrangementincorporating this function is described below.

Feedback Control Shaping Function to Pulse Driving Waveform

FIG. 23 generally illustrates a pulse driver as one example of a pulsedriving device with a feedback control shaping function for pulsedriving waveform. FIGS. 25A and 25B are timing diagrams illustratingoperation of the pulse driver of FIG. 23, particularly, the gradientcharacteristic of transition. FIGS. 24A and 24B illustrate in detail anamount of phase delay.

As shown in FIG. 23, in a pulse driver 600, a voltage V1 defining thehigh level voltage of the driving pulse is input to a terminal 601, anda voltage V2 defining the low level voltage of the driving pulse isinput to a terminal 602. An input pulse Pin at a logic level (forexample, 0 V/5 V or 0 V/3 V) supplied from a pulse signal generator (notshown) is input to a terminal 603, and a load 609 having a capacitivereactance or an inductive reactance is connected to a terminal 604. Anoutput pulse Pout appears at a terminal 604.

The pulse driver 600 includes a phase delay adjuster 610, a through rateadjuster (variation characteristic adjuster) 630, and a load driver 650.The phase delay adjuster 610 adjusts a delay timing of the input pulsePin input at the logic level from the terminal 603, namely, a phasedelay amount (one of transient characteristics of the output pulsewaveform at the terminal 604 as a junction to the load 609). The throughrate adjuster 630 adjusts a through rate indicating variations in thetransient characteristics of the output pulse waveform at the terminal604 as the junction to the load 609 while generating a prior stagedriving signal P30 in response to a control signal P10 from the phasedelay adjuster 610. The load driver 650 drives the load 609 in responseto a prior stage driving signal P30 from the through rate adjuster 630.The load driver 650 applies to the load 609 the output pulse Pout inresponse to capability corresponding to the prior stage driving signalP30 supplied from the through rate adjuster 630.

The phase delay adjuster 610, the through rate adjuster 630, and theload driver 650 constitute a waveform shaping processor 660 thatperforms a predetermined waveform shaping process to the input pulsesignal.

The pulse driver 600 includes a drive pulse waveform shaping controller670. The drive pulse waveform shaping controller 670 monitors the outputpulse waveform at the terminal 604, and controls the adjustment functionof the phase delay adjuster 610 and the through rate adjuster 630 basedon the monitoring results. The pulse driver 600 thus performs feedbackcontrol so that active transient characteristics, such as a delay timeof the output pulse Pout at the terminal 604 responsive to the inputpulse Pin, and a through rate at transition, converge to targettransient characteristics.

The drive pulse waveform shaping controller 670 includes a phase delaycontroller 672 serving as a functional element controlling the phasedelay adjuster 610, and a through rate controller 674 serving afunctional element controlling the through rate adjuster 630.

The phase delay controller 672 performs feedback control. Morespecifically, the phase delay controller 672 supplies a delay amountcontrol signal P72 to the phase delay adjuster 610 so that a delayamount of the output pulse Pout responsive to the input pulse Pinconverges to a target value (typically so that a deviation to the valuestated in specifications becomes zero) while monitoring the output pulsePout at the terminal 604.

The through rate controller 674 performs feedback control. Morespecifically, the through rate controller 674 supplies a through ratecontrol signal P74 to the through rate adjuster 630 so the through rateindicating the variation characteristic of the output pulse Poutconverges to a target value (typically so that a deviation to the valuestated in specifications becomes zero) while monitoring the output pulsePout at the terminal 604.

The phase delay adjuster 610 delays the input pulse Pin input via theterminal 603 by a duration of time externally or internally set, andsupplies the delayed control signal P10 to the through rate adjuster630.

The phase delay adjuster 610 may handle the once set delay amount as afixed amount. Alternatively, the phase delay adjuster 610 maydynamically adjust the delay amount (in response to the current state)in response to the delay amount control signal P72 from the phase delaycontroller 672 in the drive pulse waveform shaping controller 670. Amechanism for adjusting the delay amount will be described later.

A variety of methods of setting the delay amount of the control signalP10 with respect to the input pulse Pin are available. As shown in FIG.24A, for example, one method manages a delay amount tpdr1 from therising edge of the input pulse Pin to a transition start point Tsr1 atthe rising edge of the output pulse Pout (pulse waveform actuallydriving the load 609) at the terminal 604, or a delay amount tpdf1 fromthe falling edge of the input pulse Pin to a transition start point Tsf1at the falling edge of the output pulse Pout.

The phase delay controller 672 may perform this method using feedbackcontrol. More specifically, the phase delay controller 672 detects timeat which the output pulse Pout actually starts transitioning, comparesthe detection result with an internally set reference value, suppliesthe delay amount control signal P72 to the phase delay adjuster 610 sothat an error becomes zero. The setting value may be updated.

As shown in FIG. 24B, another method manages a delay amount tpdr2 fromthe rising edge of the input pulse Pin to a predetermined voltage pointTsr2 in the rising edge of the output pulse Pout (at a midpoint betweenthe voltage V1 and the voltage V2) or a delay amount tpdf2 from thefalling edge of the input pulse Pin to a predetermined voltage pointTsf2 in the falling edge of the output pulse Pout.

During the feedback control, the phase delay controller 672 detects timefrom the start of the transition of the output pulse Pout to thepredetermined voltage point Tsr2 or Tsf2, compares the detected resultwith a reference value internally or externally set, and supplies thedelay amount control signal P72 to the phase delay adjuster 610 so thatan error converges to zero. The setting value may be updated.

In the former method of FIG. 24A, the transition start points Tsr1 andTsf1 of the active pulse waveform at the terminal 604 need to beidentified. As shown in FIG. 24A, the pulse mildly changes asrepresented by broken line, and it is difficult to accurately measurethe transition start points Tsr1 and Tsf1. In the latter method of FIG.24B, the measurement of the predetermined voltage points Tsr2 and Tsf2that are relatively stable subsequent to the start of the transition iseasy to perform.

In either way, the delay amounts tpdr1 and tpdr2 and the delay amountstpdf1 and tpdf2 may be commonly or separately set.

The through rate adjuster 630 adjusts the amplitude of the prior stagedriving signal P30 to be supplied to the load driver 650, therebyadjusting the through rate at a point (terminal 604) where the loaddriver 650 drives the load 609.

More specifically, upon detecting an output transition (the start of therising edge or the falling edge) of the delay-amount adjusted controlsignal P10 output from the phase delay adjuster 610, the through rateadjuster 630 supplies to the load driver 650 the prior stage drivingsignal P30 having characteristics corresponding to the load drivingcapability of the load driver 650. When the load driver 650 drives theload 609, the prior stage driving signal P30 is used to cause the outputpulse Pout at the terminal 604 to have target through ratecharacteristic taking into consideration the relationship between theload driver 650 and the load 609. If the load 609 is not only aresistance but also a capacitive reactance or an inductive reactance, anintegrating effect is involved. As shown in FIGS. 24A and 24B, and FIGS.25A and 25B, a signal applied to the load 609 becomes typicallydifferent from the original output pulse Pout.

The through rate adjuster 630 handles the through rate once set as afixed one. Alternatively, the through rate adjuster 630 may dynamicallyadjust the through rate (in an active state) in response to the throughrate control signal P74 from the through rate controller 674 in thedrive pulse waveform shaping controller 670. A mechanism for adjustingthe through rate will be described later.

A variety of methods are available to set the through rate to thecontrol signal P10. As shown in FIG. 25A, for example, one method maymanage variation characteristic (through rate) SRr1 from a voltage at arising edge start point Tsr1 of the output pulse Pout to a voltage at arising edge end point Ter1, or variation characteristic (through rate)SRf1 from a voltage at a falling edge start point Tsf1 of the outputpulse Pout to a voltage at a falling end point Tef1.

As shown in FIG. 25B, another method may manage variation characteristic(through rate) SRr2 between two predetermined voltage points Tsr2 (atapproximately lower one-third level of the voltage between V1 and V2)and Ter2 (at approximately upper one-third level of the voltage betweenV1 and V2) of the rising edge of the output pulse Pout or variationcharacteristic (through rate) SRf2 between two predetermined voltagepoints Tsf2 (at approximately upper one-third level of the voltagebetween V1 and V2) and Tef2 (at approximately lower one-third level ofthe voltage between V1 and V2) of the output pulse Pout of the fallingedge of the output pulse Pout.

The through rate controller 674 performs one of these methods duringfeedback control. More specifically, the through rate controller 674detects an amount equal to a rate of change between these two voltagesof the output pulse Pout, compares the detection result with a referencevalue set internally or externally, and supplies the through ratecontrol signal P74 to the through rate adjuster 630 so that the errorbecomes zero. The setting value may be updated.

In the former method of FIG. 25A, the transition start points Tsr1 andTsf1 and the transition end points Ter1 and Tef1 of the active pulsewaveform at the terminal 604 need to be identified. As with thedifficulty with the identifying the rising edge delay amount tpdr1 andthe falling edge delay amount tpdf1, the accurate measurement of thestart points and the end points is difficult. It should be noted thatthe output pulse Pout may mildly start the rising edge and the fallingedge as represented by broken lines in FIG. 25A, and that high-frequencynoise may be induced in the vicinity of the transition start points. Inthe latter method of FIG. 25B, corresponding to the rising time delayamount tpdr2 and the falling time delay amount tpdf2, variationcharacteristic between the two voltages that are stable subsequent tothe start of the transition is easily identified.

In either case, the rising edge through rates SRr1 and SRr2 and thefalling edge through rates SRf1 and SRf2 may be commonly or separatelyset.

The phase delay controller 672 may estimate the transition start pointTsr1 of the rising edge and the transition end point Tsf1 of the fallingedge of the output pulse Pout based on the through rate SRr2 between thepredetermined two voltages in the rising edge of the output pulse Poutand the through rate SRf2 between the predetermined two voltages in thefalling edge of the output pulse Pout, determined by the through ratecontroller 674. In the output pulse Pout illustrated on a right portionof FIG. 25B, the transition start point Tsr1 of the rising edge and thetransition start point Tsf1 of the falling edge are found in linesextended from lines used to determine the through rates SRr2 and SRf2.

In the present embodiment, the feedback control is performed on thedelay amount and the variation characteristic (through rate at thetransition) of the output pulse Pout at the terminal 604 with respect tothe input pulse Pin. If strictly controlling both the delay amount andthe variation characteristic is not necessary, the feedback control maybe performed on one of the delay amount and the variationcharacteristic.

If the delay amount at the rising edge and the delay amount at thefalling edge vary unevenly, the through rate is also affected.Conversely, the through rate may change the rising edge characteristicand the falling edge characteristic, and as a result, the delay amountis affected. In practice, the delay amount and the variationcharacteristic mutually affect each other. The feedback control is thuspreferably performed on both the delay amount and the variationcharacteristic.

In the pulse driver 600, the load driver 650 drives the load 609. Thedrive pulse waveform shaping controller 670 monitors the active outputpulse Pout at the terminal 604 and performs the feedback control so thatthe transition characteristics of the output pulse Pout, such as thedelay amount and the variation characteristic of the output pulse Poutwith respect to the input pulse Pin, become target values.

The transition characteristic of the output pulse Pout is designed to befree from variations in the manufacture of the load 609 and variationsin the manufacture of the driving element arranged at the output stageof the load driver 650. The load 609 is thus pulse driven at optimumtransition characteristic. Furthermore, the transition characteristic isdesigned to be free from environmental changes such as temperaturechange and humidity change.

The driving capability of the load driver 650 and the characteristics ofthe load 609 (equivalent input capacitance and equivalent inputinductance) may change in response to parasitic components unpredictableat design stage (such as parasitic capacitance and parasiticinductance), variations in manufacture of the load 609, andenvironmental changes such as temperature change or humidity change. Inthat case, the delay amount of the output pulse Pout with respect to theinput pulse Pin and the gradient of the output pulse Pout may beadjusted so that the transition characteristics of the driving output(such as the delay amount and the through rate) fall within thespecifications.

With the mechanism of the present embodiment, the driving signal has aconstant delay amount and a constant gradient in the driving circuit ofthe reactance load regardless of the variations in the loadcharacteristic and the driving characteristic and the environmentalchange. Even if the output timing is determined to meet requirements ofthe load 609 in system specifications, a driving waveform has a highdegree of repeatability with a minimum error within the range ofspecifications of the delay amount and the through rate.

Load Driver for Capacitive Reactance Load

FIG. 26 is a block diagram of the load driver 650 that is an example ofthe pulse driver 600 of FIG. 23. The load driver 650 drives the load 609having a capacitive reactance. FIG. 27 is a timing diagram illustratingoperation of the pulse driver 600 of FIG. 26.

When the load 609 is a capacitive reactance load, the load driver 650includes a current output circuit to current drive the load 609. Thethrough rate adjuster 630 is designed so that the prior stage drivingsignal P30 appropriate for current driving by the load driver 650 issupplied to the load driver 650.

More specifically, the through rate adjuster 630 includes current outputsections 632_H and 632_L. The current output sections 632_H and 632_Loutput to the load driver 650 prior stage driving signal P30_H and priorstage driving signal P30_L mutually complementary to each other, andrepresenting a reference current Is determining the gradient of therising edge or the falling edge of the output pulse Pout.

The load driver 650 includes a current mirror circuit 652_H and acurrent mirror circuit 652_L. Upon receiving the voltage V1 defining thevoltage at a high level supplied to the terminal 601, the current mirrorcircuit 652_H outputs a constant current Io to the terminal 604. Uponreceiving the voltage V2 defining the voltage at a low level supplied tothe terminal 602, the current mirror circuit 652_L sinks the constantcurrent Io from the terminal 604. In other words, the load driver 650 iscomposed of a pair of upper and lower current mirror circuits 652_H and652_L.

An output stage 652_Hout of the current mirror circuit 652_H and anoutput stage 652_Lout of the current mirror circuit 652_L are connectedto each other at a junction 656 (corresponding to a current adder),which is in turn connected to the load 609 via the terminal 604. Aninput stage 652_Hin of the current mirror circuit 652_H is connected toa current output section 632_H of the through rate adjuster 630, and aninput stage 652_Lin of the current mirror circuit 652_L is connected toa current output section 632_L of the through rate adjuster 630.

The through rate adjuster 630 is separately supplied with a controlsignal P10_H corresponding to the delay amount at the rising edge and acontrol signal P10_L corresponding to the delay amount at the fallingedge.

The through rate adjuster 630 supplies the input stage 652_Hin of thecurrent mirror circuit 652_H with the prior stage driving signal P30_Hresponsive to the control signal P10_H via the current output section632_H, and the input stage 652_Lin of the current mirror circuit 652_Lwith the prior stage driving signal P30_L responsive to the controlsignal P10_L via the current output section 632_L.

With this arrangement, the through rate adjuster 630 outputs to the loaddriver 650 the prior stage driving signals P30_H and P30_L representingthe reference current Is determining the gradient of the rising edge orthe falling edge of the output pulse Pout. The load driver 650,including the pair of upper and lower current mirror circuits 652_H and652_L, multiplies the reference current Is of each of the rising edgeand the falling edge generated by the through rate adjuster 630, by aconstant (xNH and xNL) while duplicating the current. The output currentIout is then supplied to the load 609 having a capacitive reactance.

In practice, an output current Iout_H (=+Io) is supplied from the upperside current mirror circuit 652_H to the load 609 (in a sourceoperation) while the lower side current mirror circuit 652_H sinks anoutput current Iout_L (=−Io) from the load 609 (in a sink operation).

The load voltage Vout generated at the terminal 604 is determined bydividing the integration of the output current Iout supplied to the load609 by a capacitance value of the load 609. As shown in FIG. 27, if aconstant current is continuously applied to the load 609 (capacitiveload) having a capacitive reactance during the transition period, theload voltage Vout linearly changes to the power supply voltage V1 of thecurrent mirror circuit 652_H or the power supply voltage V2 of thecurrent mirror circuit 652_L.

When the load voltage Vout reaches the power supply voltage V1, theoutput stage 652_Hout of the upper side current mirror circuit 652_Hloses its constant current feature, and is connected to the power supplyvoltage V1 via the equivalent resistor thereof. The load voltage Vout isthus fixed to the power supply voltage V1. When the load voltage Voutreaches the power supply voltage V2, the output stage 652_Lout of thelower side current mirror circuit 652_L loses its constant currentfeature, and is connected to the power supply voltage V2 via theequivalent current thereof. The load voltage Vout is thus fixed to thepower supply voltage V2.

As the prior stage driving signal P30_H supplied from the current outputsection 632_H of the through rate adjuster 630 to the current mirrorcircuit 652_H, the reference current Is is reliably supplied to theinput stage 652_Hin during a period from the start of the rising edge ofthe output pulse Pout until the load voltage Vout reaches the powersupply voltage V1 (in practice, in the sink operation), and the supplyof the reference current Is to the input stage 652_Hin stops before thecurrent mirror circuit 652_L starts to operate.

As the prior stage driving signal P30_L supplied from the current outputsection 632_L of the through rate adjuster 630 to the current mirrorcircuit 652_L, the reference current Is is reliably supplied to theinput stage 652_Lin during a period from the start of the falling edgeof the output pulse Pout until the load voltage Vout reaches the powersupply voltage V2 (in practice, the source operation), and the supply ofthe reference current Is to the input stage 652_Lin stops before theupper side current mirror circuit 652_H starts to operate.

The variation characteristic of the output pulse Pout, namely, the loadvoltage Vout is defined by the driving current Io supplied to the load609 (source current Io and sink current Io), the driving current Io isdefined by the reference current Is output from the current outputsections 632_H and 632_L of the through rate adjuster 630 (sink currentIs and source current Is), and the reference current Is is defined bythe through rate control signal P74. During the feedback control, thevariation characteristic of the load voltage Vout (through rate) isvaried by adjusting the through rate control signal P74.

The load 609 is constructed of a capacitive reactance. The capacitivereactance load is driven in response to the constant current Io by thecurrent mirror circuits 652_H and 652_L during the output transitionperiod. The drive pulse waveform shaping controller 670 monitors theoutput pulse Pout, thereby performing the feedback control. Under thecontrol of the phase delay controller 672, the load voltage Vout of theoutput pulse Pout has a constant delay amount to the input pulse Pin.Under the control of the through rate controller 674, the load voltageVout of the output pulse Pout is transitioned at a constant throughrate.

The driving circuit for driving the capacitive reactance load of FIG. 26thus causes the driving signal (load voltage signal) to have a constantdelay and to transition at a constant gradient regardless of variationsin the load capacitance and the driving characteristic and environmentalchanges. Even if the output timing is determined to meet requirements ofthe load 609 in system specifications, a driving waveform has a highdegree of repeatability with a minimum error within the range ofspecifications of the delay amount and the through rate.

Load Driver for Inductive Reactance Load

FIG. 28 is a block diagram of the load driver 650 that is an example ofthe pulse driver 600 of FIG. 23. The load driver 650 drives the load 609having an inductive reactance. FIG. 29 is a timing diagram illustratingoperation of the pulse driver 600 of FIG. 28.

The driving circuit for driving the load 609 having the inductivereactance is a voltage output circuit for voltage driving the load 609as opposed to the current driving for the load 609 having the capacitivereactance. The through rate adjuster 630 is designed to supply the loaddriver 650 with the prior stage driving signal P30 appropriate for thevoltage driving by the load driver 650.

More specifically, the through rate adjuster 630 includes voltage outputsection 633_H and 633_L for outputting prior stage driving signals P30_Hand P30_L mutually complementary to each other and representing areference voltage Vs determining the gradient of the rising edge or thefalling edge of the output pulse Pout.

The load driver 650 includes a constant voltage output circuit 653_H anda constant voltage output circuit 653_L. Upon receiving a current I1defining a current at high level to be supplied to a terminal 601, theconstant voltage output circuit 653_H supplies a constant voltage V0 toa terminal 604. Upon receiving a current I2 defining a current at lowlevel supplied to a terminal 602, the constant voltage output circuit653_L supplies a constant voltage V0 to the terminal 604. The loaddriver 650 is thus composed of a pair of upper and lower constantvoltage output circuits 653_H and 653_L.

A circuit for applying a voltage V1 to the terminal 601 to supply theconstant current I1 to the constant voltage output circuit 653_H may bearranged. A circuit for applying a voltage V2 to the terminal 602 tosupply the constant current I2 to the constant voltage output circuit653_L may be arranged.

A voltage adder 657 may be arranged between an output stage 653_Hout ofthe constant voltage output circuit 653_H and an output stage 653_Loutof the constant voltage output circuit 653_L. The voltage adder 657 addsthe upper voltage to the lower voltage and supplies the voltage sum tothe terminal 604. An input stage 653_Hin of the constant voltage outputcircuit 653_H is connected to the voltage output section 633_H of thethrough rate adjuster 630. An input stage 653_Lin of the constantvoltage output circuit 653_L is connected to the voltage output section633_L of the through rate adjuster 630.

A load current detector 658 is arranged between the load driver 650 andthe load 609. With the load current detector 658, the drive pulsewaveform shaping controller 670 monitors a load driving current betweenthe load driver 650 and the terminal 604. The drive pulse waveformshaping controller 670 thus performs feedback control so that the activetransition characteristics such as the delay time and the through rateof the output pulse Pout at the terminal 604 with respect to the inputpulse Pin during transition converge to target transitioncharacteristics.

The load current detector 658 simply transfers a detected signalresponsive to the load driving current to the drive pulse waveformshaping controller 670. As shown in the functional block diagram of FIG.28, the load current detector 658 may perform one of a variety ofmethods including directly detecting a current with a currenttransformer, or using a current-to-voltage conversion function forinserting a current detecting resistor in line and detecting voltages atboth ends of the resistor. If the current itself is detected, the drivepulse waveform shaping controller 670 converts the detected current intoa voltage signal.

If the vertical driver is constructed of an integrated circuit (IC), itis difficult to include a current transformer in the IC. Including allrelated wirings into the IC is difficult. In practice, the currenttransfer is arranged between the terminal 604 and the load 609, and thedetected signal is then supplied to the drive pulse waveform shapingcontroller 670 in the IC. The current detecting resistor, if employed,may be inserted between the voltage adder 657 and the terminal 604, andall related wirings may be contained into the IC.

The constant voltage output circuits 653_H and 653_L, as opposed to thecurrent mirror circuits 652_H and 652_L, multiplies input voltages tothe input stages 653_Hin and 653_Lin by a constant number, and thenoutputs the resulting voltages from the output stages 653_Hout and653_Lout, respectively. Any circuit arrangement is acceptable as long asthis function is performed.

With this arrangement, the through rate adjuster 630 outputs to the loaddriver 650 the prior stage driving signals P30_H and P30_L representingthe reference voltage Vs and determining the gradient of the rising edgeor the falling edge of the output pulse Pout. The load driver 650,composed of the upper side and lower side constant voltage outputcircuits 653_H and 653_L, multiplies the reference voltage Vs of each ofthe rising edge and the falling edge generated by the through rateadjuster 630, by a constant (xNH and xNL) while duplicating the voltage.The output voltage Vout is then supplied to the load 609 having aninductive reactance.

In practice, the upper side constant voltage output circuit 653_Hprovides the load 609 with an output voltage Vout_H (=+Vo) (in a sourceoperation) while the lower side constant voltage output circuit 653_Lprovides the load 609 with an output voltage Vout_L (=−Vo) (in a sinkoperation).

A load current Iout generated at the terminal 604 is obtained bydividing the integration of the output voltage Vout supplied to the load609 by an inductance value of the load 609. If a constant voltage iscontinuously applied to the load 609 having an inductive reactanceduring the transition period as shown in FIG. 29, the load current Ioutchanges linearly until the load current Iout reaches the power supplycurrent I1 of the constant voltage output circuit 653_H or the powersupply current 12 of the constant voltage output circuit 653_L.

When the load current Iout reaches the power supply current I1, theoutput stage 653_Hout of the upper side constant voltage output circuit653_H loses the constant voltage feature thereof, and is connected tothe power supply current I1 via the equivalent resistance thereof. Theload current Iout is thus fixed to the power supply current I1.Conversely, if the load current Iout reaches the power supply currentI2, the output stage 653_Lout of the constant voltage output circuit653_L loses the constant voltage feature thereof, and is connected tothe power supply current I2 via the equivalent resistance thereof. Theload current Iout is thus fixed to the power supply current I2.

As the prior stage driving signal P30_H to be supplied from the voltageoutput section 633_H of the through rate adjuster 630 to the constantvoltage output circuit 653_H, any voltage is acceptable as long as thereference voltage Vs is reliably supplied to the input stage 653_Hinfrom the start point of the rising edge of the output pulse Pout untilthe load current Iout reaches the power supply current I1 (in a sinkoperation, in practice), and the supply of the reference voltage Vs tothe input stage 653_Hin stops before the lower side constant voltageoutput circuit 653_L starts to operate.

As the prior stage driving signal P30_L to be supplied from the voltageoutput section 633_L of the through rate adjuster 630 to the constantvoltage output circuit 653_L, any voltage is acceptable as long as thereference voltage Vs is reliably supplied to the input stage 653_Linfrom the start point of the falling edge of the output pulse Pout untilthe load current Iout reaches the power supply current I2 (in a sourceoperation, in practice), and the supply of the reference voltage Vs tothe input stage 653_Lin stops before the upper side constant voltageoutput circuit 653_H starts to operate.

The load 609 is an inductive reactance load. The inductive reactanceload 609 is thus driven by the constant voltage output circuits 653_Hand 653_L in response to the constant voltage V0 during the outputtransition period while the drive pulse waveform shaping controller 670performs the feedback process while monitoring the output pulse Pout.Under the control of the phase delay controller 672, the load currentIout of the output pulse Pout is controlled to have a constant delaytime. Under the control of the through rate controller 674, the loadcurrent Iout of the output pulse Pout is controlled to transition at aconstant through rate.

The driving circuit for driving the inductive reactance load of FIG. 28thus causes the driving signal (load current signal) to have a constantdelay and to transition at a constant gradient regardless of variationsin the load inductance and the driving characteristic and environmentalchanges. Even if the output timing is determined to meet requirements ofthe load 609 (such as a motor winding) in system specifications, adriving waveform has a high degree of repeatability with a minimum errorwithin the range of specifications of the delay amount and the throughrate.

Construction of Phase Delay Adjuster and Through Rate Adjuster

FIG. 30 illustrates mainly a phase delay adjuster 610 and a through rateadjuster 630 of the pulse driver 600 of FIG. 23. FIG. 31 is a timingdiagram illustrating the operation of the pulse driver 600 of FIG. 30.

The load driver 650 has the same structure as the load driver 650 ofFIG. 26 for driving the load 609 having a capacitive reactance. The samephase delay adjuster 610 and through rate adjuster 630 may be used ifthe load driver 650 has the same structure as the load driver 650 ofFIG. 28 for driving the load 609 having the inductive reactance.

The pulse driver 600 includes a terminal 605 for receiving a clocksignal CK. The phase delay adjuster 610 includes a pulse delay circuit612 and a delay clock count register 614. The pulse delay circuit 612delays an input pulse Pin (logic input) input to a terminal 603 by thenumber of clocks externally set, by referencing the clock signal CKinput to the terminal 605. The delay clock count register 614 stores thenumbers of clock (delay clock counts) defining the delay amounts of thepulse delay circuit 612, namely, the rising edge delay amount and thefalling edge delay amount. The delay clock count register 614 sets thestored delay clock counts CKD_H and CKD_L on the pulse delay circuit612.

As shown in FIG. 31, the rising edge delay amount tpdr (tpdr1 in FIG.31) is obtained by dividing the delay clock count CKD_H (=N1) by afrequency fCLK of the clock signal CK (namely, N1/fCLK). The fallingedge delay amount tpdf (tpdf1 in FIG. 31) is obtained by dividing thedelay clock count CKD_L (=N2) by a frequency fCLK of the clock signal CK(namely, N2/fCLK). Since the delay amount is adjusted by a digital valuesuch as the clock count, the adjustment is easy.

The pulse delay circuit 612 outputs an active high control signal P10_H(=Vs1) and an active high control signal P10_L (=Vs1) logically invertedfrom the control signal P10_H. The control signal P10_H rises at pointdelayed from the rising edge of the input pulse Pin by the delay amounttpdr and falls at point delayed from the falling edge of the input pulsePin by the delay amount tpdf.

The delay clock count register 614 can continuously supply the pulsedelay circuit 612 with the set delay clock counts CKD_H and CKD_L suchas register initial setting values CKD_Hini and CKD_Lini internally orexternally set. Alternatively, the delay clock counts KCD_H and CKD_Lmay be dynamically adjusted in response to the delay amount controlsignal P72 from the phase delay controller 672 of the drive pulsewaveform shaping controller 670. The register initial setting valuesCKD_Hini and CKD_Lini may be stored on the delay clock count register614 or may be set from the outside.

The term “dynamically” means that the delay clock counts may depend onthe detection result of the delay amount of the actual output pulse Poutat the terminal 604 with respect to the input pulse Pin (the actualmeasured value or estimated value). The phase delay controller 672increases or decreases the delay clock counts CKD_H and CKD_L with thedelay amount control signal P72 so that the actual delay amountcontinuously remains to be a target delay amount.

During the feedback control, the delay amount is adjusted on a digitalvalue such as the clock count. Since control information to control thephase delay adjuster 610 is handled in digital data, the adjustmentbecomes easy.

The through rate adjuster 630 includes a digital-to-analog (DA)converter 634_H and switch 636_H for rising edge control, and a DAconverter 634_L and switch 636_L for falling edge control.

The through rate adjuster 630 further includes a DAC data register 638for storing reference data DAC_H and DAC_L defining the referencecurrent Is for the DA converters 634_H and 634_L. The DAC data register638 sets stored reference data DAC_H and DAC_L on the DA converters634_H and 634_L. The DA converters 634_H and 634_L generate referencecurrents (Is on the source side and Is on the sink side) correspondingto the set reference data DAC_H and DAC_L. The reference currents on thesource side and the sink side may or may not be the same in absolutevalue.

The current output section 632_H of FIG. 26 (not shown in FIG. 30) isarranged in the output stage of the DA converter 634_H. The currentoutput section 632_L of FIG. 26 (not shown on FIG. 30) is arranged inthe output stage of the DA converter 634_L.

The DAC data register 638 can supply the DA converters 634_H and 634_Lwith the set reference data DAC_H and DAC_L such as the register initialsetting values DAC_Hini and DAC_Lini. The reference data DAC_H and DAC_Lmay be dynamically adjusted in response to the through rate controlsignal P74 from the through rate controller 674 in the drive pulsewaveform shaping controller 670. The register initial setting valuesDAC_Hini and DAC_Lini may be internally pre-stored on the DAC dataregister 638 or may be set from the outside.

The term “dynamically” means that the delay clock counts may depend onthe detection result of the through rate of the actual output pulse Poutat the terminal 604 with respect to the input pulse Pin. The throughrate controller 674 increases or decreases the reference data DAC_H andDAC_L in response to the through rate control signal P74 so that theactual through rate remains to be a target value.

The output pulse Pout, namely, the variation characteristic of the loadvoltage Vout is defined by the driving currents Io (source current Ioand sink current Io) supplied to the load 609, the driving current Io isdefined by the reference currents Is (sink current Is and source currentIs) output from the DA converters 634_H and 634_L, and the referencecurrent Is is defined by the reference data DAC_H and DAC_L. Thevariation characteristic (through rate) of the load voltage Vout variesdependent on the driving current Io.

During the feedback control, the driving current Io during transition ofthe load voltage supplied to the load 609 is adjusted on a digital valuesuch as the DAC data. The through rate of the load voltage Vout is thusadjusted. Since control information to control the through rate adjuster630 is handled in digital data, the adjustment becomes easy.

Only when the switches 636_H and 636_L are on, the through rate adjuster630 supplies the current mirror circuits 652_H and 652_L in thecorresponding load driver 650 with the prior stage driving signals P30_Hand P30_L generated by the DA converters 634_H and 634_L (the referencecurrent Is herein).

The pulse delay circuit 612 inputs to a control input terminal of theswitch 636_H a switch control signal Vs1 as the control signal P10_Hcorresponding to the delay amount at the rising edge, and to a controlinput terminal of the switch 636_L a switch control signal Vs2 as thecontrol signal P10_L corresponding to the delay amount at the fallingedge.

The DA converters 634_H and 634_L have sufficient definition, thedefinition covering variations in the driving capability of the loaddriver 650 and characteristic of the load 609, the variations attributedto variations in the manufacture of the load 609, variations in themanufacture of the driving element for use as an output stage of theload driver 650, and environmental changes such as temperature changeand humidity change. More preferably, the DA converters 634_H and 634_Lhave definition compatible with a variety of loads 609.

The pulse delay circuit 612 drives the control signal P10_H (=Vs1)active high with a delay tpdr1 from the rising edge of the input pulsePin. The output voltage Vout at the terminal 604 rises in response tothe high level of the control signal P10_H.

When the input pulse P10_H (=Vs1) from the pulse delay circuit 612 istransitioned from low to high, the switch 636_H in the through rateadjuster 630 is turned on, and the prior stage driving signal P30_Hdefining the reference current Is generated by the DA converter 634_H issupplied to the current mirror circuit 652_H in the load driver 650 (ina sink operation).

The current mirror circuit 652_H supplies the load 609 having acapacitive reactance with the driving current Io that is obtained bymultiplying the reference current Is indicated by the prior stagedriving signal P30_H (by NH times). The load voltage Vout is thentransitioned from low level to high level at a constant through rate.When the load voltage Vout reaches the power supply voltage V1, theinput stage 652_Hout in the current mirror circuit 652_H loses theconstant current feature thereof even though the reference current Is iscontinuously supplied to the input stage 652_Hin in the current mirrorcircuit 652_H. The load 609 is connected to the power supply voltage V1via the equivalent resistance thereof, and the load voltage Vout isfixed to the power supply voltage V1.

When the input pulse Pin rises afterward, the above operation isperformed in the opposite way. More specifically, the pulse delaycircuit 612 drives the control signal P10_H (=Vs1) low with a delayamount tpdf1 from the falling edge of the input pulse Pin while drivingthe control signal P10_L active high at the same time. In response, theload voltage Vout at the terminal 604 rises at the high level of thecontrol signal P10_L.

When the input pulse Pin_L (=Vs2) from the pulse delay circuit 612 istransitioned from low to high, the switch 636_L in the through rateadjuster 630 is turned on. The prior stage driving signal P30_L definingthe reference current Is generated by the DA converter 634_L is suppliedto the current mirror circuit 652_L in the load driver 650 (in a sourceoperation).

The current mirror circuit 652_L supplies to the load 609 having thecapacitive reactance the driving current Io that is obtained bymultiplying the reference current Is indicated by the prior stagedriving signal P30_L (by NH times). In this way, the load voltage Voutis transitioned from high level to low level at a constant through rate.When the load voltage Vout reaches the power supply voltage V2, theoutput stage 652_Lout in the current mirror circuit 652_L loses theconstant current feature thereof even though the reference current Is iscontinuously supplied to the input stage 652_Lin in the current mirrorcircuit 652_L. The load 609 is connected to the power supply voltage V2via the equivalent resistance thereof, and the load voltage Vout isfixed to the power supply voltage V2.

Modification of the Through Rate Adjuster

FIG. 32 illustrates mainly a modification of the phase delay adjuster610 and the through rate adjuster 630 (of FIG. 30) of the pulse driver600 of FIG. 23.

The load driver 650 has the same structure as the load driver 650 ofFIG. 26 for driving the load 609 having a capacitive reactance. The samephase delay adjuster 610 and through rate adjuster 630 may be used ifthe load driver 650 has the same structure as the load driver 650 ofFIG. 28 for driving the load 609 having the inductive reactance.

The modification shown in FIG. 32 is different from the pulse driver 600of FIG. 30 in that a DA converter 634 in the through rate adjuster 630permits two step adjustment for coarse tuning and fine tuning by DAconverters 634A and 634B.

DA converters 634A_H and 634A_L for coarse tuning generate coarsereference current Is_Coarse (Is_Hcrs and Is_Lcrs) corresponding todriving capability coarse tuning set value DAC_Coarse (coarse DAC dataDAC_Hcrs and DAC_Lcrs) set from the outside, and supply the coarsereference current Is_Coarse (Is_Hcrs and IS_Lcrs) to the DA converters634B_H and 634B_L for fine tuning. The coarse DAC data is not affected(not controlled) by the through rate control signal P74 from the throughrate controller 674, and the DA converters 634A_H and 634A_L generatethe coarse reference current Is_Coarse responsive to the drivingcapability coarse tuning set value regardless of the through ratecontrol signal P74 from the through rate controller 674.

The DA converters 634B_H and 634B_L for fine tuning generate referencecurrents (Is on the source side and Is on the sink side) set by the DACdata register 638 based on the through rate control signal P74 whilereferencing the coarse reference current Is_Coarse generated by the DAconverters 634A_H and 634A_L. In this case, the reference data DAC_H andDAC_L correspond to the driving capability fine tuning set valueDAC_Fine responsive to the driving capability coarse tuning set valueDAC_Coarse.

When the reference current Is is generated by referencing the coarsereference current Is_Coarse, one of a multiplication method and anaddition method may be used. In the multiplication method, with thecoarse reference current Is_Coarse generated by the DA converters 634A_Hand 634A_L used as a reference current, the reference current Is isgenerated by adjusting an amplification factor in accordance with thereference data DAC_H and DAC_L. In the addition method, fine referencecurrents Is_Fine (Is_Hfine and Is_Lfine) corresponding to the referencedata DAC_H and DAC_L are generated at the DA converters 634B_H and634B_L and the fine reference currents Is_Fine are added to the coarsereference Is_Coarse generated by the DA converters 634A_H and 634A_L.

Whether to use one or both of the two methods may be determined based onthe driving capability and tendency in variations. Although there aresome exceptions, the multiplication method provides a wider dynamicrange than the addition method, and the DA converters 634B_H and 634B_Lpreferably have a circuit arrangement for the multiplication method.

Regardless of the multiplication method or the addition method, thecoarse reference current Is_Coarse is free from the effect of thethrough rate control signal P74 during the feedback control, and thethrough rate of the load voltage Vout is mainly adjusted by the DAconverters 634B_H and 634B_L for fine tuning.

Even a single stage of DA converter 634 can have sufficient definition,the definition covering variations in the driving capability of the loaddriver 650 and characteristic of the load 609, the variations attributedto variations in the manufacture of the load 609, variations in themanufacture of the driving element for use as an output stage of theload driver 650, and environmental changes such as temperature changeand humidity change. More preferably, the DA converters 634_H and 634_Lhave definition compatible with a variety of loads 609.

In practice, however, the variations due to a variety of loads 609 islarge in comparison with variations in the manufacture of the load 609,variations in the manufacture of the driving element for use as anoutput stage of the load driver 650, and environmental changes such astemperature change and humidity change. The use of a single stage of DAconverter 634 is not practicable because of the unrealistic definitionthereof.

In terms of system design, the specifications of characteristics of theload 609 in use (including input equivalent capacitance, inputequivalent inductance, and driving frequency) are generally known. Ifthe DA converter 634A for coarse tuning is used taking intoconsideration the characteristics, a target driving capability may beachieved.

If the DA converter 634B for fine tuning is designed to perform feedbackcontrol to cope with variations in service, the through rate may bedynamically adjusted with a realistic definition. More specifically,with an intended driving capability set for the DA converter 634A forcoarse tuning, the driving capability and the characteristics of theload 609 (such as the input equivalent capacitance) may change becauseof parasitic capacitance, variations in the manufacturing process, andtemperature change, each unpredictable at the design stage. In thiscase, there is a possibility that the through rate of the driving outputfails to satisfy the specifications. But by controlling the DA converter634B for fine tuning with the through rate controller 674, the gradientof the output is adjusted so that the output through rate specificationsmay be satisfied.

Structure of Drive Pulse Waveform Shaping Controller

FIG. 33 illustrates mainly a drive pulse waveform shaping controller 670of the pulse driver 600 of FIG. 23. FIG. 34 is a timing diagramillustrating the operation of the pulse driver 600 of FIG. 33.

The phase delay adjuster 610 and the through rate adjuster 630 hereinare identical to the counterparts of FIG. 32. The load driver 650 isidentical to the counterpart of FIG. 26 for driving the load 609 havingthe capacitive reactance, or the counterpart of FIG. 28 for driving theload 609 having the inductive reactance. The previous discussion of thephase delay adjuster 610 and the through rate adjuster 630 is alsoequally applicable.

The drive pulse waveform shaping controller 670 includes two comparators682 and 684 and a determiner 686 forming the phase delay controller 672and the through rate controller 674. The two comparators 682 and 684 anda delay amount control function part of the determiner 686 constitutethe phase delay controller 672. The two comparators 682 and 684 and athrough rate control function part of the determiner 686 constitute thethrough rate controller 674. Alternatively, the two comparators 682 and684 and the determiner 686 may be separately arranged from the phasedelay controller 672 and the through rate controller 674.

The comparators 682 and 684 serve as a voltage comparator for comparingthe load voltage Vout with a reference voltage Vref. One input terminalof each of the comparators 682 and 684 receives the output pulse Pout ata terminal 604.

A first reference voltage Vref1 corresponding to a predetermined voltagebetween the high level voltage and the low level voltage of the outputpulse Pout at the terminal 604 is input to the other input terminal ofthe comparator 682. A second reference voltage Vref2 (>Vref1)corresponding to a predetermined voltage between the high level voltageand the low level voltage of the output pulse Pout at the terminal 604is input to the other input terminal of the comparator 684.

As shown in FIG. 34A, the two reference voltages Vref1 and Vref2 are setto appropriate voltages between voltages taken by the load voltage Vout(upper power supply voltage V1 and lower power supply voltage V2). Forexample, the first reference voltage Vref1 is at the level of aboutone-third of the voltage swing from V1 between V1 and V2, and the secondreference voltage Vref2 is at the level of about two-thirds of thevoltage swing from V1 between V1 and V2.

The comparators 682 and 684 compare the two voltage inputs in responseto the clock signal CK input from the outside via a terminal 605, andsupplies the comparison result to the determiner 686. More specifically,the comparators 682 and 684 compare the reference voltage Vref1 andVref2 to convert the analog voltage signal of the output pulse Pout intoa digital signal. Along with the comparison process, the comparators 682and 684 perform a counting process using the clock signal CK. Inresponse to the count at the moment the comparison process has ended,the comparators 682 and 684 acquire digital data representing two pointsin the transition process of the output pulse Pout. This process isreferred to as a single slop integration type AD conversion or a rampsignal comparison type AD conversion.

The comparators 682 and 684 include, respectively, voltage comparators682A and 684A for comparing the reference voltages Vref1 and Vref2 withthe output pulse Pout, and counters (CNTs) 682B and 864B for countingthe clock signal CK until the voltage comparators 682A and 684A end thecomparison process.

In the comparators 682 and 684 thus constructed, the voltage comparators682A and 684A compare the reference voltages Vref1 and Vref2 with theslope portion of the output pulse Pout. If the two voltages become equalto each other, the comparator outputs of the voltage comparators 682 and684 are reversed.

The counters 682B and 684B start the counting process in synchronizationwith the clock signal CK at the rising edge or the falling edge of theinput pulse Pin input to the terminal 603. When the voltage comparators682A and 684A notify of information indicating the reversal of thecomparator outputs, the counting process stops. The count at that momentis latched as comparison data. In other words, the time of the slope ofthe output pulse Pout is measured using the two voltage comparators 682Aand 684A.

Obtained as counts are a count Nsr2 identifying a voltage point Tsr2(corresponding to the reference voltage Vref1), a count Ner2 identifyinga voltage point Ter2 (corresponding to the reference voltage Vref2) inthe rising edge process of the output pulse Pout, a count Nsf2identifying a voltage point Tsf2 (corresponding to the reference voltageVref2) and a count Nef2 identifying a voltage point Tef2 (correspondingto the reference voltage Vref1) in the falling edge process of theoutput pulse Pout.

Measured in this way are the clock counts (counts Nsr2, Ner2, Nsf2, andNef2) within the period from the rising edge or the falling edge of theinput pulse Pin until the output reversal of the two comparators 682Aand 684A, namely, until the load voltage Vout generated by the load 609in response to the input pulse Pin reaches each of the referencevoltages Vref1 and Vref2. The comparators 682 and 684 supplies themeasured counts to the determiner 686.

The determiner 686 calculates, by clock periods, a delay amount to apredetermined voltage point along the slope of the output pulse Pout(load voltage Vout) and time required to transition between thereference voltages Vref1 and Vref2 based on the relationship of each ofthe counts Nsr2, Ner2, Nsf2, and Nef2 to the input pulse Pin calculatedby the comparators 682 and 684. The determiner 686 thus identifies thedelay amount and the through rate of the active output pulse Pout withrespect to the input pulse Pin, and controls the phase delay adjuster610 using the delay amount control signal P72 and the through rateadjuster 630 using the through rate control signal P74 so that the delayamount and the through rate converge to the target values thereof.

As shown in FIG. 34B, the average of the counts Nsr2 and Ser2 becomes adelay clock count CKD_H (=NH) representing time from the rising edge ofthe input pulse Pin to a middle voltage point between the referencevoltages Vref1 and Vref2 of the output pulse Pout. The delay amounttpdr2 is obtained by dividing the delay clock count CKD_H by thefrequency fCLK of the clock signal CK (NH/fCLK).

The average of the counts Nsf2 and Nef2 becomes a delay clock countCKD_L (=NL) representing time from the falling edge of the input pulsePin to a middle voltage point between the reference voltages Vref1 andVref2 of the output pulse Pout. The delay amount tpdf2 is obtained bydividing the delay clock count CKD_L by the frequency fCLK of the clocksignal CK (NL/fCLK).

The difference between the counts Nsr2 and Ner2 represents the throughrate SRr2 at the rising edge, and the difference between the counts Nsf2and Nef2 represents the through rate SRf2 at the falling edge.

Counts representing the upper side power supply voltage V1 and the lowerside power supply voltage V2 along an extension line of two pointsrepresenting the two reference voltages Vref1 and Vref2 defining thethrough rate SRr2 can be estimated using the counts Nsr2 and Ner2 asshown in FIG. 34C. In other words, the count Nsr1 identifying the risingedge start point Tsr1 and the count Ner1 identifying the rising edge endpoint Ter1 can be estimated. The count Nsr1 becomes the delay clockcount CKD_H (=N1) representing time from the rising edge of the inputpulse Pin to the rising edge start point Tsr1 of the output pulse Pout.The delay amount tpdr1 at the rising edge is obtained by dividing thedelay clock count CKD_H by the frequency fCLK of the clock signal CK(N1/fCLK).

As shown in FIG. 34C, counts representing the upper side power supplyvoltage V1 and the lower side power supply voltage V2 along an extensionline of two points representing the two reference voltages Vref1 andVref2 defining the through rate SRf2 can be estimated using the countsNsf2 and Nef2. In other words, the count Nsf1 identifying the risingedge start point Tsf1 and the count Nef1 identifying the rising edge endpoint Tef1 can be estimated. The count Nsf1 becomes the delay clockcount CKD_L (=N2) representing time from the falling edge of the inputpulse Pin to the falling edge start point Tsf1 of the output pulse Pout.The delay amount tpdf1 at the falling edge is obtained by dividing thedelay clock count CKD_L by the frequency fCLK of the clock signal CK(N2/fCLK).

The determiner 686 increases or decreases set values of the delay clockcount register 614 (delay clock counts CKD_H and CKD_L) using the delayamount control signal P72 and increases or decreases the set values ofthe DAC data register 638 (reference data DAC_H and DAC_L) using thethrough rate control signal P74 so that the transition characteristicsof the identified active output pulse Pout (the delay amount and thethrough rate to the input pulse Pin) converge to the target valuesstated in the specifications.

The control information to control the phase delay adjuster 610 and thethrough rate adjuster 630 is handled as digital data. Furthermore, thetransition characteristics of the activated output pulse Pout are alsodigitally measured or digitally estimated. Since the entire feedbackcontrol system is handled using digital data, measurement and adjustmentare easy.

First Configuration Applied to Vertical Driver

FIG. 35 illustrates a first configuration in which the above-describedpulse driver 600 is applied to a vertical driver 50 driving the verticaltransfer electrode 12 of the CCD solid-state image pickup element 10.Since the load driver 650 drives the vertical transfer electrode 12 ofthe capacitive reactance in this case, the structure of FIG. 26 is used.The phase delay adjuster 610 and the through rate adjuster 630 are theones of FIG. 30.

As shown in FIG. 35, the image pickup device 1 includes a CCDsolid-state image pickup element 10, a vertical transfer driver 7 fordriving a plurality of vertical transfer electrodes 12 as a capacitivereactance, a horizontal transfer driver 8 for driving a plurality ofhorizontal transfer registers 14 as a capacitive reactance in the CCDsolid-state image pickup element 10.

The vertical transfer driver 7 includes vertical drivers 700 of the samenumber as the vertical transfer electrodes 12 for separately driving thevertical transfer electrodes 12_1 through 12 _(—) z (z is the number ofphases, and for example, z=4 for four phases). The vertical transferdriver 7 thus includes the vertical drivers 700 of the same number asthe number of vertical transfer electrodes 12. The vertical transferelectrodes 12 are thus driven on a phase by phase basis. The verticaldrivers 700 are supplied in a single package semiconductor IC.

As shown in FIG. 35, vertical transfer electrodes 12_1 through 12 _(—) zarranged in the CCD solid-state image pickup element 10 are respectivelyrepresented by equivalent input capacitances C12_1 through C12_z (eachwithin a range of 100 to 1000 pF, for example). The CCD solid-stateimage pickup element 10 is a capacitive reactance load if viewed fromthe vertical driver 700.

The equivalent input capacitance C12 shows one electrode only in FIG.4A. More in detail, a serial circuit of the equivalent input capacitance12 with a wiring resistance (of several tens of Ω to several hundreds ofΩ) and a grounding resistance (of several tens of Ω) is formed.

The image pickup device 1 includes a timing signal generator 810 forgenerating a pulse signal controlling the each vertical driver 700 inthe vertical transfer driver 7 and the horizontal transfer driver 8, ananalog front end (AFE) section 820 for performing an analog signalprocess, and a video signal processor 830. The video signal processor830 includes a video calculation and processing unit 832 including adigital signal processor (DSP) for performing a predetermined videoprocess on pickup data, a video recorder 834 for storing, on apredetermined memory, video picked up by the CCD solid-state imagepickup element 10, and a video display 836 for displaying the videopicked up by the CCD solid-state image pickup element 10.

FIG. 35 illustrates the most appropriate example of the image pickupdevice 1 (CCD image pickup system). The structure of the image pickupdevice 1 may be subject to change depending on requirement ofsemiconductor process and design requirement of the entire camera. Thepresent invention is not limited to this example. All functionalelements illustrated in FIG. 35 may or may not be included in the imagepickup device 1. Part of functional elements (for example, the videodisplay 836 for monitoring) may be removed from the system. Functionalresponsibility may be freely organized among the functional elements.For example, the horizontal transfer driver 8 and the timing signalgenerator 810 may be integrated into one unit.

The image pickup device 1 may further include a mechanism shutter forstopping the storage of signal charge in the sensor section (chargegenerator) in the CCD solid-state image pickup element 10, an opticalsystem including a lens for collecting an optical image of a subject andan image capturing lens having an aperture diaphragm adjusting theamount of light of the optical image, and a controller for controllingthe entire image pickup device 1 (although these elements are notshown). The timing signal generator 810 may contain the controller.

The controller includes a central processing unit (CPU) The CPU reads acontrol program stored on a magnetic disk, an optical disk, amagneto-optical disk, or a semiconductor memory by controlling a drive(not shown), and generally controls the image pickup device 1 inaccordance with the read control program or a command input by a user.

The controller includes an exposure controller for controlling theshutter and the aperture diaphragm keeping the brightness of an imagetransferred to the video signal processor 830 to an optimum level, andan operation unit through which the user enters a shutter timing andother commands.

The CPU controls the timing signal generator 810 connected to a bus ofthe image pickup device 1, the video signal processor 830 and theexposure controller. The timing signal generator 810 and the videosignal processor 830 receive a system clock and other control signalsfrom the CPU.

The timing signal generator 810 supplies the vertical transfer driver 7and the horizontal transfer driver 8 with a variety of pulse signalsrequired to drive the CCD solid-state image pickup element 10 fortransfer operation while supplying the analog front end section 820 withpulse signals for correlated double sampling and AD conversion.

In response to the pulse signal supplied from the timing signalgenerator 810, the analog front end section 820 performs predeterminedanalog signal processes such as correlated double sampling on thecaptured image signal output from the output amplifier 16 in the CCDsolid-state image pickup element 10, converts the processed analog imagesignal into digital data, and supplies the resulting digital data to thevideo signal processor 830.

The video calculation and processing unit 832 includes the digitalsignal process (DSP) for performing the predetermined digital videoprocess on the captured image data input from the analog front endsection 820.

The video recorder 834 includes a memory (storage medium) such as flashmemory storing the video data, and a CODEC (code/decode orcompression/decompression) for encoding the video data processed by thevideo calculation and processing unit 832, and storing the encoded videodata on the memory, or reading the video data, decoding the read videodata, and supplying the decoded video data to the video calculation andprocessing unit 832 (although these element are not shown).

The video display 836 includes a digital-to-analog converter forconverting the video data processed by the video calculation andprocessing unit 832 into an analog signal, a video monitor composed of aliquid-crystal display (LCD) functioning as a viewfinder displaying theimage corresponding to the input video signal, and a video encoder forencoding the analog video signal into a video signal compatible with thesubsequent stage video monitor.

The vertical driver 700 for the vertical transfer electrode 12 hassubstantially the same structure as the pulse driver 600 of FIG. 33. Thevertical driver 700 includes a phase delay adjuster 710 corresponding tothe phase delay adjuster 610, a through rate adjuster 730 correspondingto the through rate adjuster 630, a load driver 750 corresponding to theload driver 650, a phase delay controller 772 corresponding to the phasedelay controller 672, and a through rate controller 774 corresponding tothe through rate controller 674. A drive pulse waveform shapingcontroller 770 includes the phase delay controller 772 and the throughrate controller 774.

The phase delay adjuster 710, the through rate adjuster 730, and theload driver 750 constitute a waveform shaping processor 760 forperforming a predetermined waveform shaping process on the input pulsesignal.

The vertical driver 700 includes terminals 701, 702, 703, 704, and 705corresponding to the terminals 601, 602, 603, 604, and 605 of the pulsedriver 600, respectively. The terminal 703 receives any of z phasevertical transfer clocks V1 through Vz, and the terminals 704 areconnected to respective vertical transfer electrodes 12_1 through 12_(—) z.

The vertical driver 700 further includes terminals 706 and 707 and aswitch 708 as a particular mechanism for driving the vertical transferelectrode 12. The terminal 706 receives a voltage VH defining thevoltage at high level of the vertical transfer pulses ΦV1-ΦVz. Theterminal 701 receives a voltage VM defining a middle level voltage ofthe vertical transfer pulse ΦV1 through ΦVz. The terminal 702 receives avoltage VL defining a low level voltage of the vertical transfer pulseΦV1 through ΦVz. The timing signal generator 810 supplies the terminals703 with vertical transfer clocks V1 through Vz of the input pulse Pinand the terminal 707 with a read clock ROG.

The vertical transfer clocks V1 through Vz are related to the transitionbetween the voltages VM and VL of the vertical transfer pulse ΦV1through ΦVz output from the vertical driver 700, and the read clocks ROGare related to the transition between the voltages VM and VH of thevertical transfer pulse ΦV1 through ΦVz.

The switch 708 is arranged between the terminal 704 and the terminal706. In response to the read clock ROG as a control pulse input via theterminal 707, the switch 708 connects the terminal 704 to the terminal706 during field shift so that the load voltage Vout at the terminal 704becomes the high-level voltage VH. More specifically, the switch 708supplies the high level voltage VH to the terminal 704 in order tosupply to the vertical transfer electrode 12 the pulse voltage which isrequired to transfer the signal charge from the photo sensor 11 in theCCD solid-state image pickup element 10 to the vertical transferregister 13.

When the vertical transfer electrodes 12 are driven by vertical transferclocks of different phases in this arrangement, the pulse output signalof the vertical transfer electrode 12 in the active state thereof ismonitored and the feedback control is performed so that each outputpulse signal has predetermined transition characteristic. Even if thereare variations in load characteristic of the vertical transfer electrode12 (equivalent input capacitance C12, in particular) from element toelement, variations in driving characteristics of the load drivers 750from element to element, and environmental changes, constant transitioncharacteristic is continuously obtained.

Appropriate driving is continuously performed in a manner free from thevariations in the manufacture of the capacitive load and theenvironmental changes. Since the variations in the transitioncharacteristic of the driving output pulse can be reduced to almostzero, high speed driving can be performed. If there are variations inthe transition characteristic, driving needs to be performed with amargin taking into account the variations. Since the driving can beperformed with the margin almost reduced to zero, high speed driving ispermitted.

The logic relationship of the vertical transfer clocks V1 through Vz,the read clocks ROG, and the voltage levels VH, VM, and VL of thevertical transfer pulse ΦV1 through ΦVz are illustrated for exemplarypurposes only. The present invention is not limited to this logicrelationship, and any logic relationship may be set depending on systemrequirements.

In the arrangement of the vertical driver 700, the above-referencedpulse driver 600 is used to generate a low speed pulse signal having aslow variation characteristic between the low level voltage VL and themiddle level voltage VM of the vertical transfer pulse ΦV1 through ΦVzbased on the vertical transfer clocks V1 through Vz supplied to theterminals 703. The switch 708 for the high level voltage VH directlyresults in the transition between the middle level voltage VM and thehigh level voltage VH based on the read clock ROG, and this arrangementdoes not necessarily provide a low speed pulse having a slow variationcharacteristic.

In the characteristic and the driving method of the CCD solid-stateimage pickup element 10, the mild slope in the transition between themiddle level voltage VM and the high level voltage VH and the transitionbetween the low level voltage VL and the high level voltage VH may beachieved using the mechanism of the pulse driver 600.

As shown in FIG. 35, identical vertical drivers 700 supplied in thesemiconductor IC are used to individually drive the vertical transferelectrodes 12 with the respective terminals 707 supplied with the readclocks ROG. Not all vertical transfer electrodes 12 need the read clockROG, and in fact, the timing signal generator 810 does not supply allvertical drivers 700 at the terminals 707 thereof with the read clocksROG.

For example, in the interline CCD solid-state image pickup element 10,V1 and V3 of the four phase vertical transfer clocks V1-V4 and the readclocks ROG are combined to form the vertical transfer pulses ΦV1 and ΦV3taking one of three levels VL, VM, and VH. The vertical transfer pulsesΦV1 and ΦV3 are used not only for the originally intended verticaltransfer operation but also signal charge reading. In all pixel readingtype CCD solid-state image pickup element 10, V1 of the three phasevertical transfer clocks V1-V3 and the read clock ROG are combined toform a vertical transfer pulse ΦV taking one of the three levels VL, VM,and VL. The vertical transfer pulse ΦV1 is used not only in theoriginally intended vertical transfer operation but in the signal chargereading operation.

Second Configuration Applied to the Vertical Driver

FIG. 36 illustrates a second configuration in which the above-referencedpulse driver 600 is applied to the vertical driver 50 driving thevertical transfer electrode 12 in the CCD solid-state image pickupelement 10. In the second configuration, the pulse driver 600 of thevertical driver 700 in the first configuration of FIG. 35 is the oneshown in FIG. 33 rather than the one shown in FIG. 30. A drive pulsewaveform shaping controller 770, corresponding to the drive pulsewaveform shaping controller 670, includes comparators 782 and 784 and adeterminer 786. The comparators 782 and 784 are simplified in FIG. 36.

A timing signal generator 810 sets register initial set values CKD_Hiniand CKD_Lini in a delay clock count register 714, a driving capabilitycoarse tuning value (coarse DAC data) in a DA converter 734A for coarsetuning, and register initial set values DAC_Hini and DAC_Lini in a DACdata register 738.

An operation controller 790 is added to control the operation of theimage pickup device 1 depending on operational status. For example, theoperation controller 790 performs control operation of the drive pulsewaveform shaping controller 770 in the vertical driver 700(corresponding to the pulse driver 600) performed to the waveformshaping processor 760.

The operation controller 790 may be mounted external to the verticaltransfer driver 7 as shown in FIG. 36. Alternatively, the operationcontroller 790 may be mounted internal to the vertical transfer driver7. In this case, if a single package IC containing each vertical driver700 is used, the operation controller 790 is contained in the samepackage IC. If the vertical drivers 700 driving the vertical transferelectrodes 12 are supplied in separate ICs, the operation controller 790is mounted in each of the vertical drivers 700. One of the operationcontrollers 790 may be selected.

The operation controller 790 receives the vertical transfer clocks V1through Vz as the input pulse Pin, clock signal CK, and videosynchronization signals from the timing signal generator 810 whilesupplying to the drive pulse waveform shaping controller 770 an outputwaveform shaping permit signal P790 controlling the operation of thedrive pulse waveform shaping controller 770. The video synchronizationsignals include a horizontal synchronization signal, a verticalsynchronization signal, and control signals controlling a variety ofimage pickup modes.

The operation controller 790 permits or stops the operation of the drivepulse waveform shaping controller 770 in response to the videosynchronization signal. A logic input specifying the polarity of theoutput pulse may be used to assist the video synchronization signal.

During standard pickup mode, the image pickup device 1 minimizes noisecomponent appearing in images by stopping the feedback control using thedrive pulse waveform shaping controller 770 within the effective pixelperiod of the CCD solid-state image pickup element 10 and by activatingthe feedback control using the drive pulse waveform shaping controller770 during only a vertical blanking period that doest not directlyappear on screen. The image pickup device 1 thus adjusts the delayamount and the through rate so that the active transition characteristicof the vertical transfer pulse driving the vertical transfer electrode12 meets the specifications.

At least time for one screen is available for system stabilization whenthe pickup mode is switched. During the effective pixel period of theone screen, the feedback control using the drive pulse waveform shapingcontroller 770 is activated. The delay time and the through rate areadjusted so that the active transition characteristic of the verticaltransfer pulse driving the vertical transfer electrode 12 meets thespecifications. Steady state can thus be quickly restored.

In addition to the video synchronization signals, the signal forcontrolling the system is supplied to the vertical driver 700 to be usedfor calculation and determination. Flexible system is easily provided.

Third Configuration Applied to the Vertical Driver (First CircuitSharing Technique to a Plurality of Loads)

FIG. 37 illustrates a third configuration in which the above-referencedpulse driver 600 is applied to the vertical driver 50 driving thevertical transfer electrode 12 in the CCD solid-state image pickupelement 10. As the first configuration of FIG. 35, the thirdconfiguration incorporates the structure of FIG. 30 as the pulse driver600. The third configuration employs a first technique that reduceshardware by sharing part of function to the plurality of verticaltransfer electrodes 12.

The first sharing technique is based on the concept that in connectionwith a logic input for driving one vertical transfer electrode 12 and alogic input for driving another vertical transfer electrode 12,adjustment values to the delay amount and the through rate to the logicinputs can be equalized if the vertical transfer electrodes 12 have thesame equivalent input capacitance C12. The drive pulse waveform shapingcontroller 770 controls the phase delay adjuster 710 and the throughrate adjuster 730 while monitoring the delay amount of the output pulsePout to the input pulse Pin and the variation characteristic (throughrate) of the output pulse Pout. That drive pulse waveform shapingcontroller 770 is shared by a plurality of vertical transfer electrodes12 having the identical equivalent input capacitance C12.

More specifically, in a vertical transfer driver 7A performing the firstsharing technique, vertical transfer electrodes 12 having identicalequivalent input capacitances C12 from among the plurality of verticaltransfer electrodes 12 used in the CCD solid-state image pickup element10 may share the structure corresponding to the pulse driver 600 exceptthe load driver 650.

More specifically, in a vertical driver 700A of the vertical transferdriver 7A, the drive pulse waveform shaping controller 770 monitors thepulse output signal on one of the plurality of vertical transferelectrodes 12 having the same characteristic, and then controls thewaveform shaping processors 760 corresponding to the plurality ofvertical transfer electrodes 12 so that the pulse output signals of theplurality of vertical transfer electrodes 12 having the samecharacteristic have the same transition characteristic.

For example, although individual load drivers 750A and 750B respectivelyconnected to two vertical transfer electrodes 12 having the sameequivalent input capacitance C12 are employed, the other elements, suchas the phase delay adjuster 710, the through rate adjuster 730, and thedrive pulse waveform shaping controller 770 are shared by the verticaltransfer electrodes 12. The through rate adjuster 730 includes, at thejunctions thereof with load drivers 750A and 750B, current distributors740A and 740B for distributing to the load drivers 750A and 750B thereference current Is represented by the prior stage driving signal P30output from the DA converter 734.

The current distributor 740 is used to distribute the reference currentIs defined by the DA converter 734 for output driving capability settinginto prior stage driving signal P30_Ha and P30_La for one verticaltransfer electrode 12 _(—) a and prior stage driving signal P30_Hb andP30_Lb for the other vertical transfer electrode 12 _(—) b.

The current Is is distributed into two with the two vertical transferelectrodes 12 having the same capacitance. Alternatively, if a pluralityof vertical transfer electrodes 12 are used, the current Is may bedistributed among the same number of electrodes.

For example, the four types of vertical transfer electrodes 12_1 through12_4 for four phase driving are arranged in FIG. 1. It is contemplatedthat the four types of vertical transfer electrodes 12_1 through 12_4are respectively driven by the respective four phase vertical drivers.Alternatively, each vertical transfer electrode may be divided into aplurality of lines, and each line may be driven by a respective verticaldriver.

For example, a functionally one vertical transfer electrode may bephysically divided into an upper half and a lower half of the imagepickup section 10 a, two output stages of the vertical driver(corresponding to the load driver 750 herein) are mounted on an upperside and a lower side of the image pickup section 10 a. The uppervertical transfer electrode is driven by the upper side output stage andthe lower vertical transfer electrode is driven by the lower side outputstage.

Since the lines of the four types of vertical transfer electrodes 12_1through 12_4 (line _a and line _b) are originally one in this case, onetarget driving timing works. A signal originated from a single inputpulse may be distributed among two output stages. The load capacitanceof distribution destinations may be different. If the signals to besupplied to the two lines (corresponding to the prior stage drivingsignal P30 to be supplied to the load driver 750 herein) are set to thesame timing, managing the driving timings subsequent to distribution isdifficult.

The lines, having originally the same pattern, also have the sameequivalent input capacitances C12_a and C12_b. When the signals derivedfrom one input pulse are distributed among the output stages of twolines, the signals to be supplied to the output stages (corresponding tothe prior stage driving signal P30 to be supplied to the load driver750) are substantially equalized.

With the first sharing technique, a vertical transfer clock V1 as alogic input 1 a is supplied to a pulse delay circuit 712 to drive twoline vertical transfer electrode 12_1 a and 12_1 b of the verticaltransfer electrode 12_1 in the vertical driver 700A in the verticaltransfer driver 7A. A read clock ROG as a logic input 2 a (if necessary)is supplied to the switch 708.

The vertical transfer driver 7A includes the same mechanism (not shown)as the vertical driver 700A to drive the other vertical transferelectrodes 12_2, 12_3, and 12_4.

The drive pulse waveform shaping controller 770 in the vertical driver700A monitors the activation state of each of the load voltage Vouthaving the same equivalent input capacitance C12 (for example, a loadvoltage Vout1 a at a vertical transfer electrode 12_1 a), and adjuststhe delay amount and the through rate responsive to the logic input.

A single waveform shaping processor 760 monitors the output of one lineof two lines, namely, the load voltage Vout1 a at the vertical transferelectrode 12_1 a (or the load voltage Vout1 b at the vertical transferelectrode 12_1 b). Adjustment is made so that the load voltage Vout1 aat the vertical transfer electrode 12_1 a has a predetermined delayamount and a predetermined through rate in response to the verticalclock V1 supplied from the timing signal generator 810 as the logicinput 1 a. Also adjustment is made so that the load voltage Vout1 b atthe vertical transfer electrode 12_1 b has a predetermined delay amountand a predetermined through rate.

The logic input 1 a (vertical transfer clock V1) is commonly used todrive the two line physically separated vertical transfer electrodes12_1 a and 12_1 b. Since the vertical transfer electrodes 12_1 a and12_1 b have the same equivalent input capacitance C12, the adjustmentamounts in the delay amount responsive to the delay amount controlsignal P72 to the phase delay adjuster 710 (more specifically the delayclock count register 714), and the through rate responsive to thethrough rate control signal P74 to the through rate adjuster 730 (morespecifically the DAC data register 738) are also the same.

The arrangement employed in the vertical transfer driver 7A forperforming the first sharing technique is effective because of thesymmetrical structure of the electrodes in the CCD solid-state imagepickup element 10. Since one equivalent input capacitance C12 isdesigned to be equal to the other equivalent input capacitance C12,circuit redundancy on the drive pulse waveform shaping controller 670 iseffectively eliminated.

When there are vertical transfer electrodes 12 having the sameequivalent input capacitance C12 in the vertical transfer driver 7A forperforming the first sharing technique, not only the drive pulsewaveform shaping controller 770 but also the phase delay adjuster 710and the through rate adjuster 730 are shared. Circuits that can beshared are not limited to these elements. A variety of modifications maybe applied to the sharing technique in the system configuration of theimage pickup device 1 and the structure and characteristic of the CCDsolid-state image pickup element 10. Such modifications are describedbelow.

Modification of the Third Configuration to the Vertical Driver

When the complementary driving of FIGS. 6A and 6B is performed, thefirst sharing technique is applicable. The drive pulse waveform shapingcontroller 770 monitors the pulse output signal occurring on one line ofthe plurality of vertical transfer electrodes 12 having the samecharacteristic. The drive pulse waveform shaping controller 770 controlsthe waveform shaping processor 760 corresponding to the plurality ofvertical transfer electrodes 12 so that the pulse output signals of theplurality of vertical transfer electrodes 12 having the samecharacteristic have the same transition characteristic.

When the interline type CCD solid-state image pickup element 10 is fourphase driven as described with reference to FIG. 2, the CCD solid-stateimage pickup element 10 includes the four types of vertical transferelectrodes 12_1 through 12_4 corresponding to the respective phases. Thefirst layer vertical transfer electrodes (second electrode) 12_2 and thefirst layer vertical transfer electrode (fourth electrode) 12_4 aresubstantially identical in pattern shape, and the second layer verticaltransfer electrode (first electrode) 12_1 and the second layer verticaltransfer electrode (third electrode) 12_3 are substantially identical inpattern shape. The first layer electrodes are different from the secondlayer electrodes in pattern shape. The equivalent input capacitancesC12_1 and C12_3 of the vertical transfer electrodes 12_1 and 12_3 aresubstantially equal to each other, and the equivalent input capacitanceC12_2 and C12_4 of the vertical transfer electrodes 12_2 and 12_4 aresubstantially equal to each other. Each of the equivalent inputcapacitances C12_1 and C12_3 is not equal to each of the equivalentinput capacitances C12_2 and C12_4.

If the vertical transfer electrodes 12 having the same equivalent inputcapacitances C12 are driven in the complementary driving method, thevertical transfer electrodes 12 having the same equivalent inputcapacitances C12 are supplied with the vertical transfer pulses changingin opposite phases. For example, in the vertical transfer driver 7A, oneof the logic inputs 1 a (vertical transfer clock V1) and 1 b (verticaltransfer clock V2) is supplied to the pulse delay circuit 612, and DAconverters 734_H and 734_L supply the outputs thereof to currentdistributors 740A and 740B. The current distributors 740A and 740Bsupply the output currents thereof to load drivers 750A and 750B. Whenthe current distributors 740A and 740B supply the output currentsthereof to the load drivers 750A and 750B, the phase of the currents maybe inverted.

More specifically, the output of the DA converter 734_H is supplied to acurrent mirror circuit 752_H in the load driver 750A and a currentmirror circuit 752_L in the load, driver 750B. The output of the DAconverter 734_L is supplied to a current mirror circuit 752_L in theload driver 750A and a current mirror circuit 752_H in the load driver750B.

With this mechanism, the reference current Is generated in response to asingle input pulse Pin using the same phase delay adjuster 710 and thesame through rate adjuster 730 is distributed in equal amounts betweenthe load driver 750A and the load driver 750B for a plurality ofvertical transfer electrodes 12. If there are no variations from oneequivalent input capacitances C12 to another during the complementarydriving, the rising edge characteristic and the falling edgecharacteristic of the two lines are accurately equalized.

Two load drivers 750, namely, a load driver 750A and a load driver 750Bmay be arranged to work with two vertical transfer electrodes 12 havingthe same equivalent input capacitance C12. Two pulse delay circuits 712in the phase delay adjuster 710, namely, pulse delay circuits 712A and712B may be arranged. Two DA converters 734, namely, DA converters 734Aand 734B, and two switches 736, namely, switches 736A and 736B may bearranged in the through rate adjuster 730.

The delay clock counts CKD_H and CKD_L set in the delay clock countregister 714 are commonly set in the individual pulse delay circuits712A and 712B in response to the delay amount control signal P72 fromthe phase delay controller 772. The reference data DAC_H and DAC_L setin the DAC data register 738 is commonly set in the individual DAconverters 734A and 734B in response to the through-rate control signalP74 from the through-rate controller 774.

In such a modification, the drive pulse waveform shaping controller 770in the vertical driver 700B monitors the activated state of one loadvoltage Vout of the vertical transfer electrodes 12 having the sameequivalent input capacitance C12 (for example, a load voltage Vout1 ofthe vertical transfer electrode 12_1). The drive pulse waveform shapingcontroller 770 then adjusts the delay amount and the through rate inresponse to the logic inputs (for example, a combination of verticaltransfer clocks V1 and V3) based on the monitoring result.

Adjustment is made so that the load voltage Vout1 a at the verticaltransfer electrode 12_1 has a predetermined delay amount and apredetermined through rate in response to the vertical clock V1 suppliedfrom the timing signal generator 810 as the logic input 1 a. Alsoadjustment is made so that the load voltage Vout1 b at the verticaltransfer electrode 12_3 has a predetermined delay amount and apredetermined through rate in response to the vertical clock V3 suppliedfrom the timing signal generator 810 as the logic input 1 b.

The logic input 1 a for driving the vertical transfer electrode 12_1(vertical transfer clock V1) and the logic input 1 b for driving thevertical transfer electrode 12_3 (vertical transfer clock V3) differentin phase are separately input. The vertical transfer electrodes 12_1 and12_3 have the same equivalent input capacitance C12. In the verticaltransfer electrodes 12_1 and 12_3, the same phase delay adjustmentquantity and the same through rate as the same load current adjustmentquantity (adjustment amount of Io) result.

The phase delay amounts at the pulse delay circuits 712A and 712B inresponse to the delay amount control signal P72 to the phase delayadjuster 710 (more specifically, the delay clock count register 714) arecontrolled to be of the same amount. The through rates at the DAconverters 734A and 734B in response to the through rate control signalP74 to the through rate adjuster 730 (more specifically, the DAC dataregister 738) are controlled to be of the same amount. For the verticaltransfer electrodes 12_1 and 12_3, the output pulses having the phasedelay amount and the through rate satisfying the specifications thusresult.

Fourth Configuration to the Vertical Driver (Second Circuit SharingTechnique to a Plurality of Loads)

FIG. 38 illustrates a fourth configuration in which the above-referencedpulse driver 600 is applied to the vertical driver 50 driving thevertical transfer electrode 12 in the CCD solid-state image pickupelement 10. Like the first configuration of FIG. 35, the fourthconfiguration employs the arrangement of FIG. 30 for the pulse driver600. The fourth configuration also provides a second circuit sharingtechnique to a plurality of vertical transfer electrodes 12.

With the second circuit sharing technique, like the first circuitsharing technique, the drive pulse waveform shaping controller 770monitors the delay amount of the output pulse Pout with reference to theinput pulse Pin and the variation characteristic (through rate) of theoutput pulse to control the phase delay adjuster 710 and the throughrate adjuster 730. The drive pulse waveform shaping controller 770 isshared by a plurality of vertical transfer electrodes 12 to reducehardware. The second circuit sharing technique is different from thefirst circuit sharing technique in that regardless of whether theequivalent input capacitances C12 are the same, the drive pulse waveformshaping controller 770 is shared and used in a time-division manner.

In a vertical driver 700C in a vertical transfer driver 7C for embodyingthe second circuit sharing technique, the drive pulse waveform shapingcontroller 770 monitors, in a time-division manner, pulse output signalsoccurring at a plurality of vertical transfer electrodes 12. The drivepulse waveform shaping controller 770 controls the waveform shapingprocessor 760 corresponding to the respective vertical transferelectrodes 12 so that the pulse output signals of the vertical transferelectrodes 12 have predetermined transition characteristics.

To use the drive pulse waveform shaping controller 770 with theplurality of vertical transfer electrodes 12 in a time-division manner,a switch 852 for selectively inputting the output of the load driver 750to the drive pulse waveform shaping controller 770 is arranged. Theinput of the switch 852 is connected to an output line extending betweenthe load driver 750 and the terminal 704, and the output of the switch852 is connected to the phase delay controller 772 and the through ratecontroller 774 in the drive pulse waveform shaping controller 770.

The drive pulse waveform shaping controller 770 further includes aswitch 854 and a switch 856. The switch 854 selectively supplies thedelay amount control signal P72 from the phase delay controller 772 tothe delay clock count register 714 in the phase delay adjuster 710. Theswitch 856 selectively supplies the through rate control signal P74 fromthe through rate controller 774 to the DAC data register 738 in thethrough rate adjuster 730.

The vertical transfer driver 7C includes a selection signal generator860 for generating selection signals P860A and P860B controlling theselection operation of the switches 852, 854, and 856. The selectionsignal generator 860 receives, from the timing signal generator 810, thelogic input 1 a (vertical transfer clock VA) for driving one verticaltransfer electrode 12A and a logic input 1 b (vertical transfer clockVB) for driving the other vertical transfer electrode 12B.

The selection signal generator 860 selects a channel to be controlled bythe drive pulse waveform shaping controller 770 (as to which verticaltransfer electrodes 12A and 12B to be waveform shaped) by activating oneof the selection signals P860A and P860B in response to the logic inputs1 a and 1 b.

More specifically, the selection signal generator 860 outputs theselection signals P860A and P860B to the switches 852, 854, and 856 toperform the selection process onto the vertical transfer electrodes 12.The selection signal P860A is input to control input terminals of theswitches 852A, 854A, and 856A related to the one vertical transferelectrode 12A. The selection signal 860B is input to control inputterminals of the switches 852B, 854B, and 856B related to the othervertical transfer electrode 12B.

The selection signal generator 860 references the logic input 1 a(vertical transfer clock VA) and the logic input 1 b (vertical transferclock VB) supplied from the timing signal generator 810 and activatesonly the selection signal P860A when the drive pulse waveform shapingcontroller 770 adjusts the delay amount and the through rate for thevertical transfer electrode 12A in the feedback control. The switches852A, 854A, and 856A are thus turned on. The selection signal generator860 activates only the selection signal P860B when the drive pulsewaveform shaping controller 770 adjusts the delay amount and the throughrate for the vertical transfer electrode 12B in the feedback control.The switches 852B, 854B, and 856B are thus turned on.

In the configuration of the vertical transfer driver 7C for performingthe second circuit sharing technique, the switches 852, 854, and 856 arearranged. The drive pulse waveform shaping controller 770 switches thechannel to be controlled in a time-division manner. The drive pulsewaveform shaping controller 770 thus monitors the delay amount of theoutput pulse Pout with respect to the input pulse Pin and the variationcharacteristic of the output pulse Pout (through rate) to control thephase delay adjuster 710 and the through rate adjuster 730. The drivepulse waveform shaping controller 770 is shared by a plurality ofvertical transfer electrodes 12. Hardware is thus reduced.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

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 9. A method of driving asemiconductor device for physical quantity distribution sensing, thesemiconductor device including, in a semiconductor substrate, chargegenerating sections arranged in a matrix for generating signal chargeresponsive to an input electromagnetic wave, a first charge transfersection for successively transferring in one direction the signal chargegenerated by the charge generating section, a second charge transfersection for successively transferring the signal charge, transferred bythe first charge transfer section, in another direction different fromthe one direction, and a charge storage section arranged between thefirst charge transfer section and the second charge transfer section,the method comprising the steps of: providing a capacitive functionalelement for making a grounding resistance of the semiconductor substratecapacitive; and transferring the signal charge of a predetermined unitin the other direction generated by the charge generating section to thecharge storage section by driving the signal charge in the one directionwithin an effective transfer period of the other direction, andtransferring the signal charge of a predetermined unit in the otherdirection transferred to the charge storage section to the second chargetransfer section by driving the signal charge outside the effectivetransfer period of the other direction.
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 15. A driving device fordriving a semiconductor device for physical quantity distributionsensing, the semiconductor device including, in a semiconductorsubstrate, charge generating sections arranged in a matrix forgenerating signal charge responsive to an input electromagnetic wave, afirst charge transfer section for successively transferring in onedirection the signal charge generated by the charge generating section,a second charge transfer section for successively transferring thesignal charge, transferred by the first charge transfer section, inanother direction different from the one direction, a charge storagesection arranged between the first charge transfer section and thesecond charge transfer section and an output section for converting thesignal charge transferred from the second charge transfer section intoan electrical signal, the driving device comprising: a driver circuitfor transferring, to the charge storage section, signal charge of apredetermined unit in the other direction generated by the chargegenerating section, by driving the signal charge in the one directionwithin an effective transfer period of the other direction, with thesemiconductor device supplied with driving signals, and transferring, tothe second charge transfer section, the signal charge of a predeterminedunit in the other direction transferred to the charge storage section bydriving the signal charge outside the effective transfer period of theother direction; and a capacitive functional element for making agrounding resistance of the semiconductor substrate capacitive. 16.(canceled)
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 19. An electronic apparatuscomprising: a semiconductor device for physical quantity distributionsensing, including, in a semiconductor substrate, charge generatingsections arranged in a matrix for generating signal charge responsive toan input electromagnetic wave, a first charge transfer section forsuccessively transferring in one direction the signal charge generatedby the charge generating section, a second charge transfer section forsuccessively transferring the signal charge, transferred by the firstcharge transfer section, in another direction different from the onedirection, a charge storage section arranged between the first chargetransfer section and the second charge transfer section and an outputsection for converting the signal charge transferred from the secondcharge transfer section into an electrical signal; a capacitivefunctional element for making a grounding resistance of thesemiconductor substrate capacitive; and a driving device including adriver circuit, the driver circuit transferring, to the charge storagesection, signal charge of a predetermined unit in the other directiongenerated by the charge generating section, by driving the signal chargein the one direction within an effective transfer period of the otherdirection, with the semiconductor device supplied with a driving signal,and transferring, to the second charge transfer section, the signalcharge of a predetermined unit in the other direction transferred to thecharge storage section by driving the signal charge outside theeffective transfer period of the other direction.
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